Researchers in Computer Architecture and Compilers

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Name	Address	Picture	Work
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Martín Abadi	Professor U of California at Santa Cruz cse.ucsc.edu/~abadi/home.html		security, programming languages, specification and verification dblp
Tarek S. Abdelrahman	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~tsa		Jasmine compiler, NUMAchine multiprocessor, POW system dblp
Mokhtar Aboelaze	Professor York U, Canada cs.yorku.ca/~aboelaze		omputer networks, mobile networks, computer architecture, special purpose architecture for image processing dblp
Jacob A. Abraham	Professor U of Texas, Austin, ECE cerc.utexas.edu/~jaa		VLSI design and test, formal verification, fault-tolerant computing dblp
Santosh G. Abraham	Sun Microsystems trimaran.org/car_group/santosh_abraham.html (old)		multiprocessor systems, optimizing compilers, performance evaluation, memory hierarchy simulation and design, Cheetah cache simulator, Trimaran, Elcor dblp
Miron Abramovici	Chief Technical Officer DAFCA Inc. bell-labs.com/user/miron (old)		CAD and testing, reconfigurable computing, FPGAs dblp
David Abramson	Professor Monash U, Australia csse.monash.edu.au/~davida		high performance computer systems design, software engineering tools for programming parallel and distributed supercomputers dblp
Shail (Gupta) Aditya	Senior Research Scientist Hewlett-Packard Labs, Compiler and Architecture Group trimaran.org/car_group/shail_aditya.html		PICO, Elcor, Id, parallel Haskell, parallel computing, compilers dblp
Ali-Reza Adl-Tabatabai	Intel MRL www-2.cs.cmu.edu/~ali		compiler optimizations, debugging dblp
Sarita Adve	Professor U of Illinois Urbana-Champaign, CS rsim.cs.uiuc.edu/~sadve		RSIM, memory consistency models dblp
Vikram S. Adve	Professor U of Illinois Urbana-Champaign, CS www-sal.cs.uiuc.edu/~vadve		link- and run-time compilation, POEMS, dHPF, compilers for distributed applications, LLVM dblp
Anant Agarwal	Professor MIT cag.lcs.mit.edu/~agarwal Maurice Wilkes (2001) award		RAW, Alewife, Virtual Wires dblp
Gul Agha	Professor U of Illinois at Urbana-Champaign, CS www-osl.cs.uiuc.edu/people?user=agha		Actors, concurrent programming, formal verification, software engineering, programming languages dblp
Dharma P. Agrawal	Professor U of Cincinnati ececs.uc.edu/~dpa		ad hoc and sensor networks, wireless and mobile networks, scheduling and task migration on NOWs, multithreaded execution of OO programs, parallelization of irregular FORTRAN loops dblp
Vishwani D. Agrawal	Professor Auburn U eng.auburn.edu/~vagrawal		SOC test, low-power VLSI design dblp
Alfred V. Aho	Professor Columbia U, CS cs.columbia.edu/~aho		compilers, AWK dblp
Alexander Aiken	Professor Stanford U, CS theory.stanford.edu/~aiken		type systems, static program analysis and abstract interpretation, constraint resolution algorithms, parallel programming, language design, domain specific languages, end user programming, visualization dblp
Anastassia Ailamaki	Professor Carnegie Mellon U, CS cs.cmu.edu/~natassa		computer architecture, databases dblp
David Al-Dabass	Professor Nottingham Trent U, UK ducati.doc.ntu.ac.uk/uksim/dad/webpage.htm		parallel and neural processing, clusters, parallel performance estimation dblp
David H. Albonesi	Professor Cornell U, ECE csl.cornell.edu/~albonesi		computer architecture, microprocessor design, power-aware microarchitecture, performance evaluation dblp
Nikitas A. Alexandridis	Professor George Washington U seas.gwu.edu/~alexan		advanced computer system architectures, high performance processors, parallel and distributed processing, computer vision and image processing/transmission, software prototyping for parallel systems & algorithms, heterogeneous computing dblp
Virgílio A. F. Almeida	Professor U Federal de Minas Gerais, Brazil dcc.ufmg.br/~virgilio		computing systems performance analysis and modeling, e-commerce dblp
Bowen Alpern	IBM T. J. Watson		Jalapeno (Java VM), SSA, theoretical models of hierarchical memory and parallelism, distributed and parallel computing, computational linear algebra dblp
Erik R. Altman	IBM T. J. Watson		DAISY, binary translation, software pipelining dblp
Rajeev Alur	Professor U of Pennsylvania cis.upenn.edu/~alur		design tools for embedded software, formal modeling and verification of reactive systems, model checking, hybrid systems, distributed computing, logic and automata theory dblp
Saman P. Amarasinghe	Professor MIT cag.lcs.mit.edu/~saman		compiler optimizations, computer architectures, software engineering, parallel computing dblp
Gene M. Amdahl	Retired chairman Commercial Data Servers Inc actscorp.com/acts/amdahl.htm Eckert-Mauchly (1987) award		pipelining, instruction look-ahead, cache dblp
Henrik Reif Andersen	Professor IT University of Copenhagen, Denmark itu.dk/people/hra		verification of concurrent and embedded systems, model checking, modal mu-calculus, models of concurrent systems, configuration problems and configuration software, implementation of embedded systems dblp
Tom Anderson	Professor U of Washington Seattle, CS cs.washington.edu/homes/tom		Internet, operating systems, scheduler activations dblp
David Andrews	Professor U of Kansas ittc.ku.edu/~dandrews		real time distributed, embedded systems, computer architecture dblp
Andrew W. Appel	Professor Princeton U cs.princeton.edu/~appel		compilers, functional programming languages dblp
James R. Armstrong	Professor Virginia Tech, EE ecpe.vt.edu/faculty/armstrong.html		modeling with hardware description languages, high level testing dblp
Mark G. Arnold	Professor Lehigh U cse.lehigh.edu/~marnold		computer architecture and arithmetic, hardware description languages dblp
Arvind	Professor MIT csg.lcs.mit.edu/Users/arvind		term-rewriting systems, dynamic dataflow, Id dblp
Krste Asanovic	Professor MIT cag.lcs.mit.edu/~krste		T0 vector microprocessor, low power, neural network implementations dblp
John Vincent Atanasoff	Professor (deceased) Iowa State U, CS cs.iastate.edu/jva/jva-archive.shtml		first digital computer
Peter M. Athanas	Professor Virginia Tech, EE ee.vt.edu/~athanas		computer architecture, VLSI, custom computing machines, parallel processing, hardware/software codesign, high-level synthesis, rapid prototyping of digital systems dblp
Darren C. Atkinson	Professor Santa Clara U cse.scu.edu/~atkinson		software engineering, compilers dblp
David I. August	Professor Princeton U, CS cs.princeton.edu/~august		compilers for predicated architectures dblp
Todd M. Austin	Professor U of Michigan eecs.umich.edu/~taustin		SimpleScalar, Diva (Dynamic Verification), microarchitecture design, low power computing, compiler design, computer system simulation and validation, performance analysis tools and techniques dblp
Eduard Ayguade	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/eduard		parallelizing compilers, OpenMP, data placement optimization, parallel computing in Java, ILP dblp
James H. Aylor	Professor U of Virginia, EE ee.virginia.edu/profile.php?ID=2		system-level modeling, concurrent error detection, automatic test pattern generation, hardware description languages, VLSI system design dblp
Adnan Aziz	Professor U of Texas, Austin, ECE ece.utexas.edu/~adnan		design and verification of digital IC dblp
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Bevan M. Baas	Professor UC Davis ECE ece.ucdavis.edu/~bbaas/		processor architecture, VLSI design, fast Fourier transform processors, low power CMOS
John Backus	computerhistory.org/events/hall_of_fellows/backus/ Turing (1977) award		FORTRAN, Backus-Naur form dblp
David F. Bacon	Researcher IBM T. J. Watson research.ibm.com/people/d/dfb/		design and implementation of programming languages, concurrent systems dblp
Wael M. Badawy	Professor U of Calgary, Canada badawy.ca		architectures for image and video processing, system on a chip dblp
Scott B. Baden	Professor UC San Diego, CS cs.ucsd.edu/users/baden		high performance and scientific computation, application-specific programming models and optimization strategies, KeLP dblp
Jean-Loup Baer	Professor U of Washington Seattle, CS cs.washington.edu/homes/baer		caches, computer architecture, programmable network interfaces dblp
Nader Bagherzadeh	Professor UC Irvine eng.uci.edu/comp.arch/nader.html		MorphoSys, multithreaded architectures, processor architecture dblp
R. Iris Bahar	Professor Brown U, ECE lems.brown.edu/iris.html		computer architecture, low-power design, CAD, nanosystem design dblp
Vasanth Bala	IBM research		parallel computation, Dynamo, dynamic optimization dblp
Thomas Ball	Microsoft Research, Software Productivity Tools research.microsoft.com/~tball		formal methods for programs dblp
Prithviraj Banerjee	Professor Northwestern U, ECE ece.nwu.edu/~banerjee		parallel algorithms for VLSI design automation, distributed memory parallel compilers, compilers for adaptive computing, PARADIGM, ProperCAD, MATCH dblp
Cristina Barrado	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/cristina		automatic parallelization dblp
Luiz André Barroso	Google barroso.org		server workloads, SimOS-Alpha dblp
Rajeev Barua	Professor U of Maryland, ECE ece.umd.edu/~barua		MAPS (Raw compiler), modulo unrolling dblp
Forest Baskett	Venture Partner New Enterprise Associates nea.com/Partners/Bios/Menlo/FBaskettBio		MIPS, SUN, DEC WRL founder dblp
Kenneth E. Batcher	Professor Kent State U, CS cs.kent.edu/~batcher Eckert-Mauchly (1990) award		parallel computers, interconnection networks dblp
Jürgen Becker	Professor U of Karslruhe www-itiv.etec.uni-karlsruhe.de/opencms/opencms/de/institute/staff/becker.html		hardware/software codesign, hardware synthesis, systems-on-a-chip dblp
Robert C. Bedichek	Transmeta Corp. bedichek.org/robert		Alewife, Meerkat, multicomputers dblp
Peter A. Beerel	Professor U of Southern California jungfrau.usc.edu/beerel.html		CAD, mixed asynchronous/synchronous VLSI design dblp
Richard A. Belgard	Consultant members.aol.com/richb89600		computer architecture
Gordon Bell	senior researcher Microsoft Bay Area Research Center research.microsoft.com/users/GBell Eckert-Mauchly (1982) award		minicomputers, timeshring, hardware description languages dblp
Luca Benini	Professor U of Bologna, Italy www-micrel.deis.unibo.it/~benini		computer-aided design of digital circuits, low-power applications, design of portable systems dblp
Siegfried Benkner	Professor U of Vienna, Austria par.univie.ac.at/~sigi		ADVANCE, AURORA, HPF+ dblp
Steve Bennett	Intel, Hillsboro intel.com/research/people/bios/bennett_s.htm		SimpleScalar, trace cache, multiscalar dblp
Alan D. Berenbaum	Agere Systems cm.bell-labs.com/cm/cs/who/adb		computer architecture, architectural support for high-speed networking, VLSI design dblp
Emery D. Berger	Professor U of Massachusetts Amherst, CS cs.umass.edu/~emery		garbage collection, virtual memory management, locality-preserving data structures, compilers for high-level optimization and error detection dblp
Neil W. Bergmann	Professor U of Queensland, Brisbane, Australia itee.uq.edu.au/~bergmann		reconfigurable computing, embedded systems infrastructure for ubiquitous computing dblp
Kees van Berkel	Philips Research, Netherlands research.philips.com/profile/people/fellows/berkel.html		asynchronous circuits, VLSI design dblp
David Bernstein	Department Manager Systems and Software, IBM Research Israel		code scheduling, optimizing compilers dblp
Gerard Berry	Professor Ecole des Mines, Paris, France www-sop.inria.fr/meije/personnel/Gerard.Berry.html		programming languages design/semantics/implementation, reactive and real-time programming, synchronous circuit design and synthesis, automatic verification of FSM, lambda calculus and its models dblp
Vaughn Betz	Altera Corp. eecg.toronto.edu/~vaughn (old)		FPGAs, CAD for FPGAS, computer architecture, VLSI design, VPR dblp
Dileep Bhandarkar	Director of Enterprise Architecture Lab Intel intel.com/pressroom/kits/bios/dbhandarkar.htm		VAX, Prism, MIPS, Alpha, memories, computer architecture dblp
Shuvra S. Bhattacharyya	Professor U of Maryland, ECE ece.umd.edu/~ssb		architectures and CAD for embedded systems, hardware/software co-design for signal/image/video processing dblp
Laxmi N. Bhuyan	Professor UC Riverside, CS cs.ucr.edu/~bhuyan		computer architecture, performance evaluation, parallel and distributed systems, interconnection networks, fault tolerant computing dblp
Ricardo Bianchini	Professor Rutgers U, CS cs.rutgers.edu/~ricardob		parallel/distributed and cluster computing, techniques for optimizing power and energy, new I/O architectures, Internet-related technologies dblp
Armin Biere	Professor ETH Zurich, Switzerland inf.ethz.ch/personal/biere		model checking, hardware verification dblp
Aart J. C. Bik	Intel liacs.nl/home/ajcbik		compilers for scientific computing, Java compilation, automatic vectorization dblp
Angelos Bilas	Professor U of Crete, Greece wwww.ics.forth.gr/~bilas		parallel architectures, programming paradigms, parallel applications, interconnection networks, block-level storage subsystems, performance analysis and evaluation, distributed systems dblp
Benjamin J. Bishop	Professor U of Scranton, CS cs.uofs.edu/~bishop		multimedia systems, computer graphics, processor architecture, VLSI design, low-power electronics, MGAP-II, SPARTA dblp
David T. Blaauw	Professor U of Michigan at Ann Arbor eecs.umich.edu/cgi-bin/fac/facsearchform.cgi?blaauw+		circuit analysis, computer-aided design, high performance design dblp
Stephen M. Blackburn	Professor Australian National U, Australia cs.anu.edu.au/~Steve.Blackburn		programming languages, dynamic cooperative performance optimization Java, transactional object storage, image processing dblp
R. D. (Shawn) Blanton	Professor Carnegie Mellon U, ECE ece.cmu.edu/~blanton		design and test of VLSI, fault-tolerant computing, computer architecture dblp
Guy E. Blelloch	Professor Carnegie Mellon U, CS cs.cmu.edu/~guyb		thread scheduling, parallel algorithms, NESL language, parallel computing dblp
Matthias Blume	Professor Toyota Technical Institute, Chicago people.cs.uchicago.edu/~blume		design and implementation of high-level programming languages, SML/NJ dblp
Matthias A. Blumrich	IBM Research cs.princeton.edu/~mb (old)		SHRIMP, shared memory multiprocessing dblp
Arndt Bode	Professor Technische U Muenchen, Germany wwwbode.cs.tum.edu/~bode		parallel and distributed architectures/applications, programming environments and tools dblp
Rastislav Bodík	Professor UC Berkeley cs.berkeley.edu/~bodik		critical path, compilers, computer architecture dblp
François Bodin	Researcher IRISA, France irisa.fr/caps/people/bodin/index_fr.htm		program optimizations, HPC programming environments, compilers, ILP, parallel computers dblp
Hans-Juergen Boehm	Hewlett-Packard Labs hpl.hp.com/personal/Hans_Boehm/		Boehm-Weiser garbage collector, gcj, multiprocessor synchronization, constructive real arithmetic dblp
Taisuke Boku	Professor U of Tsukuba, Japan arch.is.tsukuba.ac.jp/~taisuke/index-e.html		network topology, data transfer methods for HPC on MPPs dblp
Shekhar Y. Borkar	Director of Circuit Research Intel intel.com/research/people/bios/borkar_s.htm		8051 microcontrollers, iWarp, high-speed signaling for supercomputers dblp
Pradip Bose	Research Staff Member IBM T. J. Watson research.ibm.com/people/b/bose		high-performance computer architectures, CAD, performance evaluation, performance verification, parallel processing, compilers, VLSI testing and verification dblp
Luc Bougé	Professor IRISA/ENS Cachan, Bretagne, France ens-lyon.fr/~bouge		semantics of languages for parallel programming, cluster computing dblp
Donald W. Bouldin	Professor U of Tennessee at Knoxville microsys6.engr.utk.edu/ece/bouldin_home.html		microelectronic systems design, adaptive computing systems, VLSI, ASICs, FPGAs, MCMs, synthesis dblp
Chandrasekhar Boyapati	Professor U of Michigan eecs.umich.edu/~bchandra		software reliability, program analysis dblp
Robert S. Boyer	Professor U of Texas, Austin, CS cs.utexas.edu/users/boyer		theorem prooving, Maxima (Macsyma clone), Boyer-Moore theorem prover, hardware verification dblp
Robert K. Brayton	Professor UC Berkeley, EE www-cad.eecs.berkeley.edu/~brayton		analysis of nonlinear networks, electrical simulation and optimization of circuits, combinational and sequential logic synthesis, asynchronous synthesis, formal verification dblp
Scott E. Breach	Hewlett-Packard cs.wisc.edu/~breach (old)		multiscalar processors dblp
Gordon J. Brebner	Professor U of Edinburgh, UK dcs.ed.ac.uk/home/gordon		flexible architecture and networking dblp
Mauricio Breternitz Jr.	Intel MRL intel.com/research/people/bios/breternitz_m.htm		parallelizing compilers multiprocessors and VLIW, binary translation, on IP telephony, parallelizing database servers dblp
Melvin A. Breuer	Professor U of Southern California poisson.usc.edu/Breuer.html		CAD, design-for-test and built-in self-test, VLSI circuits dblp
Faye A. Briggs	director of chipset architecture Intel Enterprise Products Group		computer architecture, parallel processing dblp
Robert W. Brodersen	Professor UC Berkeley, ECE bwrc.eecs.berkeley.edu/People/Faculty/rb		low power design, wireless communications, CAD tools dblp
Stephen D. Brookes	Professor Carnegie Mellon U, CS csd.cs.cmu.edu/research/faculty_research/brookes.html		semantics of programming languages, trace semantics dblp
David Brooks	Professor Harvard U eecs.harvard.edu/~dbrooks		interaction architecture/software/hardware, power dissipation and chip cooling modelling, Wattch dblp
Frederick P. Brooks Jr.	Professor U of North Carolina, CS cs.unc.edu/~brooks Turing (1999) award, von Neumann medal (1993), National Medal of Technology (1985), Allen Newell (1994) award, Eckert-Mauchly (2004) award		3D interactive computer graphics, human-computer interaction, virtual worlds, molecular graphics, IBM S/360, STRETCH, The Mythical Man-Month dblp
Mats Brorsson	Professor Royal Institute of Technology, Stockholm, Sweden it.kth.se/~matsbror		energy aware architectures, shared address space multiprocessors, programming models for parallel programs, software DSM dblp
Angela Demke Brown	Professor U of Toronto, CS, Canada cs.toronto.edu/~demke		compiler-guided resource management, run-time adaptation, operating systems, compiler optimization, parallel and distributed systems dblp
Donna J. Brown	Professor U of Illinois at Urbana-Champaign, ECE wocket.csl.uiuc.edu/~djb		VLSI layout, combinatorial algorithms, parallel and distributed algorithms and architecture, Web-based instruction, Mallard dblp
Richard B. Brown	Dean, College of Engineering U of Utah coe.utah.edu/brown		IC design (VLSI), solid-state chemical sensors, MEMS, mixed-signal circuits, high-performance, radiation-hard and low-power microprocessors, CMOS/SOI/GaAs dblp
Stephen Dean Brown	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~brown		FPGAs, CAD, place and route dblp
Erik Brunvand	Professor U of Utah, CS cs.utah.edu/~elb/home.html		computer architecture, VLSI systems, self-timed and asynchronous systems dblp
Randal E. Bryant	Professor Carnegie Mellon U, CS cs.cmu.edu/~bryant		Binary Decision Diagrams (BDD), formal verification, model checking dblp
Mihai Budiu	Microsoft Research cs.cmu.edu/~mihaib (old)		reconfigurable hardware, optimizing compilers, spatial computation dblp
Duncan A. Buell	Professor U of South Carolina cse.sc.edu/~buell		Splash 2 reconfigurable system, numeric computations, parallel algorithms and architectures, computational number theory dblp
Doug Burger	Professor U of Texas, Austin, CS cs.utexas.edu/users/dburger		SimpleScalar, Datascalar, memory systems dblp
Neil Burgess	Professor Cardiff U, UK engin.cf.ac.uk/whoswho/profile.asp?RecordNo=138		computer arithmetic, digital signal processing, hardware support for DSP dblp
Wayne P. Burleson	Professor U of Massachusetts Amherst ECE ecs.umass.edu/ece/vspgroup/burleson.html		VLSI signal processing, on-chip interconnects, reconfigurable computing dblp
Martin Burtscher	Professor Cornell U, ECE csl.cornell.edu/~burtscher		high-performance microprocessor architecture, ILP, compiler optimizations, value prediction, data compression, latency-reduction techniques dblp
Rajkumar Buyya	Professor Monash U, Australia buyya.com		computer architecture, operating systems, compilers, parallel / distributed / cluster / grid / peer-to-peer computing dblp
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George Z. N. Cai	Engineering manager Intel Design Center, Texas		power modeling and management, microprocessor design and implementation dblp
Brad Calder	Professor UC San Diego www-cse.ucsd.edu/users/calder		prediction, mobile code, PSSA dblp
Timothy J. Callahan	post-doc Carnegie Mellon U, CS www-2.cs.cmu.edu/~tcal		GARP, reconfigurable hardware compilation, system-on-a-chip design automation, hardware/software codesign dblp
João M. P. Cardoso	Professor U of Algarve, Portugal w3.ualg.pt/~jmcardo		reconfigurable computing, high-level synthesis for FPGAs, design automation for embedded systems dblp
Douglas M. Carmean	principal engineer/architect Intel Desktop Products, Oregon		IA-32, Pentium, Pentium 4 dblp
Steven M. Carr	Professor Michigan Technological U, CS cs.mtu.edu/~carr		high-level optimization for DSP, compilers-computer architecture interaction, concurrent computing dblp
John B. Carter	Professor U of Utah, CS cs.utah.edu/~retrac		operating systems, parallel and distributed computing, multiprocessor computer architecture, memory system design, Munin dblp
Lori Carter	Professor Point Loma Nazarene U, San Diego mcs.ptloma.edu/Carter		computer architecture, compiler optimizations, predicated execution, compilation for IA64 dblp
Nicholas P. Carter	Professor U of Illinois Urbana-Champaign, ECE crhc.uiuc.edu/~npcarter		reconfigurable logic, computing using non-silicon dblp
Calin Cascaval	IBM T. J. Watson polaris.cs.uiuc.edu/~cascaval (old)		parallel compilers, parallel and distributed computing, object oriented compilers and methodologies dblp
Steve Casselman	Virtual Computer Corp		reconfigurable computing, search engines dblp
Gregory J. Chaitin	IBM T. J. Watson cs.umaine.edu/~chaitin		register allocation, algorithmic information theory dblp
Craig Chambers	Professor U of Washington Seattle, CS cs.washington.edu/homes/chambers		SPIN, dynamic compilation, Vortex, Cecil dblp
Fay Chang	Google cs.cmu.edu/~fwc (old)		Speculative prefetching for disk data, distributed filesystems dblp
J. Morris Chang	Professor Iowa State U, EE vulcan.ee.iastate.edu/~morris		wireless network, computer architecture, object-oriented programming languages, memory management, hardware description languages, internet architecture dblp
Craig M. Chase	Professor U of Texas, Austin, ECE ece.utexas.edu/~chase		parallel architectures and algorithms dblp
Siddhartha Chatterjee	Professor U of North Carolina, CS cs.unc.edu/~sc		cache-conscious algorithms, data parallelism dblp
Tiberiu Chelcea	postdoc Carnegie Mellon U, CS cs.cmu.edu/~tibi		asynchronous circuits dblp
Peter M. Chen	Professor U of Michigan eecs.umich.edu/~pmchen		RIO, ARMADA, fault tolerance, disk systems dblp
Tien-Fu Chen	Professor National Chung Cheng U, China cs.ccu.edu.tw/~chen		computer architecture, SOC design, embedded systems dblp
Fu-Chiung John Cheng	Professor Tatung U, Taiwan cse.ttu.edu.tw/~cheng		Systems-on-a-chip, hardware-software codesign, CAD tools, asynchronous logic, FPGAs, Java-enabled embedded systems, real-time OS, expert database systems dblp
Perry Cheng	IBM T.J. Watson research.ibm.com/people/p/perryche		garbage collection, type-directed compilation dblp
David R. Cheriton	Professor Stanford U www-dsg.stanford.edu/DavidCheriton.html		distributed systems, high performance networks, operating systems, distributed interactive simulation, object-oriented design techniques dblp
Peter Y. K. Cheung	Professor Imperial College, London, UK ee.ic.ac.uk/pcheung		reconfigurable computing, hardware/software codesign, CAD, Digital and Asynchronous Systems, VLSI architecture for signal processing, mixed signal designs dblp
Men-Chow Chiang	IBM Server Group		memory systems for multiprocessors dblp
Donald M. Chiarulli	Professor U of Pittsburgh, EE cs.pitt.edu/~don		chip level optoelectronic interconnections, optical-electronic-mechanical multi-domain CAD, optical memory systems, robotics, SOC voice based interfaces dblp
Andrew A. Chien	Professor UC San Diego www-csag.ucsd.edu/individual/achien/achien.html		Agile Distributed Objects, High Performance Virtual Machines (HPVM), Illinois Concert Project, QoS management dblp
Bruce R. Childers	Professor U of Pittsburgh, CS cs.pitt.edu/~childers		automatic design of application-specific processors, custom VLIW/systolic architectures, low-power embedded processors, computer architecture, compilers and software development tools dblp
Trishul M. Chilimbi	Microsoft Research research.microsoft.com/~trishulc		optimizations for caching dblp
Giovanni Chiola	Professor U di Genova, Italy disi.unige.it/person/ChiolaG		active messages (GAMMA), distributed databases dblp
Derek Chiou	Professor U of Texas at Austin ECE ece.utexas.edu/~derek		simulators, sequential and parallel computer architectures, router architecture, dataflow machines, StarT dblp
Jong-Deok Choi	IBM Research T. J. Watson research.ibm.com/people/j/jdchoi		programming languages, compiler optimizations, software engineering dblp
Kiyoung Choi	Professor Seoul National U, Korea poppy.snu.ac.kr/~kchoi/kchoi.html		VLSI design, CAD, hardware-software codesign, high-level synthesis, low-power system design dblp
Frederic T. Chong	Professor UC Davis, CS american.cs.ucdavis.edu:80/~chong		Active Pages dblp
Pai H. Chou	Professor UC Irvine ece.uci.edu/~chou		IMPACCT, embedded systems, low power design dblp
Alok N. Choudhary	Professor Northwestern U ECE ece.northwestern.edu/~choudhar		compilers and runtime systems for high-performance embedded/adaptive/power-aware systems, high-performance databases, parallel and high-performance storage and I/O systems dblp
Fred C. Chow	Pathscale, Inc.		optimizing compilers dblp
Paul Chow	Professor U of Toronto, EE, Canada eecg.toronto.edu/~pc		FPGAs, OneChip, Transmogrifier-2 dblp
Giuseppe Ciaccio	Professor U di Genova, Italy disi.unige.it/person/CiaccioG		clusters of PCs, operating systems, parallel processing, parallel computer architecture dblp
Michal Cierniak	researcher Intel Microprocessor Research Labs, Programming Systems Lab intel.com/research/mrl/people/cierniak_m.htm		virtual machines, runtime systems, just-in-time compilation, high-performance compiler optimizations dblp
Marcelo H. Cintra	Professor U of Edinburgh, UK dcs.ed.ac.uk/home/mc		computer architectures, parallel and high-performance computing, scientific computing dblp
Douglas W. Clark	Professor Princeton U, CS cs.princeton.edu/~doug		processor architecture and organization, performance measurement and analysis, computer architecture, Display Wall dblp
Wesley A. Clark	Clark, Rockoff and Associates Eckert-Mauchly (1981) award		design of early computers, TX-0, TX-2 dblp
Edmund M. Clarke	Professor Carnegie Mellon U, CS cs.cmu.edu/~emc		formal verification, model checking dblp
John G. Cleary	Professor U of Waikato, New Zealand cs.waikato.ac.nz/Staff/john-g.-cleary.html		parallel and distributed systems, TimeWarp, compression, logic programming dblp
Cliff Click	Motorola crpc.rice.edu/MSCP/cliff.html (old)		compiler optimizations, intermediate program representations dblp
John Cocke	(deceased) IBM T. J. Watson Eckert-Mauchly (1985) award, Turing (1987) award		optimizing compilers, RISC processors dblp
Robert S. Cohn	Intel		Alpha compilers, profile-feedback compilation, Spike, code layout in Unix OM dblp
Michele Colajanni	Professor U di Modena, Italy traianus.ce.uniroma2.it/people/colajanni.html		distributed parallel computing, distributed web servers, parallel scientific computing, fault-tolerance, interconnection networks, performance analysis and simulation dblp
Osvaldo Colavin	ST Microelectronics		architectural support for multimedia dblp
Jean-Francois Collard	Intel prism.uvsq.fr/~jfcollar (old)		automatic parallelization, optimizing compilers dblp
Robert P. Colwell	Colwell and Associates, Inc. Eckert-Mauchly (2005) award		Pentium Pro, Multiflow dblp
Hubert Comon-Lundh	Professeur Ecole Normale Superieure de Cachan, France lsv.ens-cachan.fr/~comon/		term rewriting, symbolic constraint solving, tree automata techniques, verification of infinite state systems, cryptographic protocols dblp
Katherine Compton	Professor U of Wisconsin-Madison ECE ece.wisc.edu/~kati/		reconfigurable computing dblp
Jason Cong	Professor U of California at Los Angeles, CS ballade.cs.ucla.edu/~cong		hardware synthesis, giga-scale system-on-a-chip, FPGAs, large-scale CAD dblp
Daniel A. Connors	Professor U of Colorado, CS cs.colorado.edu/~dconnors		high performance computer systems, run-time optimization architectures, embedded systems, optimizing compilers, operating systems dblp
Charles Consel	Professor ENSEIRB/LaBRI/INRIA Bordeaux, France compose.labri.u-bordeaux.fr/people/consel		programming languages, program analysis and transformation, software engineering, operating systems dblp
Thomas M. Conte	Professor North Carolina State U, ECE tconte.org		compiler design, advanced microarchitectures, VLIW/IA-64 compilers dblp
Lynn Conway	Professor (emeritus) U of Michigan ai.eecs.umich.edu/people/conway/conway.html		VLSI, robotics/AI dblp
Stephen A. Cook	Professor U of Toronto, CS, Canada cs.toronto.edu/~sacook Turing (1982) award		NP-completeness, computational complexity, logic dblp
William R. Cook	Professor U of Texas at Austin, CS cs.utexas.edu/users/wcook		programming languages, mixins, type theory, object-oriented programming, interfacing languages and databases, software engineering, web-based information systems, information security dblp
Keith D. Cooper	Professor Rice U, CS cs.rice.edu/~keith		Rn, ParaScope, low-level code optimization, code generation, GrDAS dblp
Lee D. Coraor	Professor Penn State U cse.psu.edu/gradbroc/faculty/coraor.html		FPGAs, SmartDIMM (computing in memory) dblp
Henk Corporaal	Professor Technische U Eindhoven, Netherlands ics.ele.tue.nl/~heco		automatic synthesis of application specific processors, very large scale distributed embedded DSP systems dblp
Jordi Cortadella	Professor U Politecnica de Catalunya, Spain lsi.upc.es/~jordic		synthesis, analysis and verification of concurrent systems, asynchronous systems, logic synthesis, Petrify dblp
Michel Cosnard	Professor/director INRIA inria.org/presse/cvmc.en.html		parallel algorithms and architectures, algorithm complexity, automata theory and neural networks, discrete dynamical systems dblp
Patrick Cousot	Professor Ecole Normale Superieure Paris, France di.ens.fr/~cousot		abstract interpretation, semantics dblp
Radhia Cousot	Research Director Ecole Polytechnique, France di.ens.fr/~cousot		abstract interpretation, semantics, proofs dblp
Alan L. Cox	Professor Rice U, CS cs.rice.edu/~alc		TreadMarks, FASTLINK dblp
Harvey G. Cragon	Professor (emeritus) U of Texas, Austin, ECE ece.utexas.edu/ece/people/profs/Cragon.html Eckert-Mauchly (1986) award		first integrated circuit computer, first TTL computer dblp
Karl Crary	Professor Carnegie Mellon U, CS cs.cmu.edu/~crary		type-oriented compilation strategies, type-based certification of mobile code, high-level programming language design dblp
John Crawford	Director of McKinley Architecture Intel Architecture Group, Enterprise Platforms Group intel.com/pressroom/kits/bios/crawford.htm Eckert-Mauchly (1995) award		IA-64, 80386, Pentium dblp
Seymour Cray	(deceased) cgl.ucsf.edu/home/tef/cray/tribute.html Eckert-Mauchly (1989) award		supercomputers
Stefano Crespi-Reghizzi	Professor Politecnico di Milano, Italy elet.polimi.it/people/crespi		formal languages and automata, compiler optimization and parallelization, programming languages, man-machine interfaces dblp
Darren C. Cronquist	Hewlett-Packard Labs, Compiler and Architecture Group hpl.hp.com/research/itc/car/Templates/darren-cronquist-page.html		architectures/compilers/languages for embedded applications, RaPiD (reconfigurable hardware), PICO dblp
Mark Crovella	Professor Boston U, CS cs-www.bu.edu/faculty/crovella		performance evaluation of parallel and networked computers, measuring and characterizing the web dblp
David E. Culler	Professor UC Berkeley, CS cs.berkeley.edu/~culler		Active Messages, Threaded Abstract Machine, parallel architectures dblp
Walling R. Cyre	Professor Virginia Tech, EE ecpe.vt.edu/faculty/cyre.html		automatic design, requirements analysis, natural language understanding, automatic modeling, high-level synthesis, design representation dblp
Ronald K. Cytron	Professor Washington U in St. Louis, CS cs.wustl.edu/~cytron		SSA, compilers, continuous compilers, packet filtering, secure voting dblp
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Ole-Johan Dahl	(deceased) Oslo U, Norway ifi.uio.no/~olejohan Turing (2001) award, von Neumann Medal (2001)		Simula, type theory, object-oriented programming dblp
Fredrik Dahlgren	Professor Chalmers U, Goteborg, Sweden ce.chalmers.se/~dahlgren		high-performance multiprocessors, multiprocessors for telecom systems dblp
William J. Dally	Professor Stanford U csl.stanford.edu/~billd Maurice Wilkes (2000) award		Imagine, J-machine, the reliable router, high-speed interconnection networks dblp
Marco Danelutto	Professor U of Pisa, Italy di.unipi.it/~marcod		parallel programming with skeletons, P3L, parallel functional, ocamlp3l, (massively) parallel architectures, ILP, Linux clusters dblp
Alain Darte	Researcher CNRS ens-lyon.fr/~darte/index-us.html		automatic parallelization, HPF, Nestor, scheduling, systolic arrays dblp
Chitaranjan R. Das	Professor Pennsylvania State U cse.psu.edu/~das		computer architecture, parallel and distributed computing, design and analysis of routing algorithms, processor management in multiprocessors, performance evaluation and fault-tolerant computing dblp
Manuvir Das	Microsoft Research research.microsoft.com/users/Manuvir/homepage.html		static program analysis, application to compilers/error detection/program verification dblp
Aravind Dasu	Professor Utah State U ece.usu.edu/ece/faculty_staff/profile.php?id=229		reconfigurable computing for media and scientific computing dblp
Edward S. Davidson	Professor (emeritus) U of Michigan eecs.umich.edu/~davidson Eckert-Mauchly (2000) award		computer architecture, supercomputing, parallel and pipelined computers, performance modeling and optimization, application code, assessment and tuning, VLSI systems, memory organization and management, CAD dblp
Jack W. Davidson	Professor U of Virginia, CS cs.virginia.edu/~jwd		zephyr, high-performance embedded applications, dynamic optimization for power dblp
Al Davis	Professor U of Utah, CS cs.utah.edu/~ald		parallel computer architecture, adaptive memory systems, asynchronous circuits and systems dblp
Nathaniel J. Davis	Professor Virginia Tech, EE ecpe.vt.edu/faculty/davisnj.html		advanced computer architectures, parallel processing, interconnection networks, computer networks, computer system simulation and performance modeling, embedded microprocessor systems dblp
Koen De Bosschere	Professor Ghent U, Belgium elis.ugent.be/~kdb		debugging of parallel programs, Java technology, link-time optimization, computer architecture dblp
Bjorn De Sutter	postdoc Gent U, Belgium elis.ugent.be/~brdsutte		binary rewriting, embedded software optimization, low-power optimization, reconfigurable computing, software protection techniques, computer architecture, program compaction dblp
Alexander G. Dean	Professor North Carolina State U cesr.ncsu.edu/agdean		computer architecture and compilation techniques for embedded systems, software thread integration dblp
Saumya K. Debray	Professor U of Arizona cs.arizona.edu/people/debray		programming languages and compilers, binary rewriting and link-time code optimization, code compression dblp
James C. Dehnert	Transmeta		compilers, Standard Template Library, Cydra 5 dblp
André DeHon	Professor Caltech U, CS cs.caltech.edu/~andre		reconfigurable hardware, DPGA, MATRIX dblp
José G. Delgado-Frias	Professor Washington State U eecs.wsu.edu/~jdelgado		VLSI microarchitectures, routers, immunity-/genetic-/neural network-based computing dblp
Robert DeLine	Microsoft Research research.microsoft.com/users/rdeline		user interfaces, software engineering, type theory, Vault dblp
James Demmel	Professor UC Berkeley, CS cs.berkeley.edu/~demmel		LAPACK, ScaLAPACK, linear systems, numerical methods dblp
Jack B. Dennis	Professor (emeritus) MIT lcs.mit.edu/people/bioprint.php3?Record_ID=26 Eckert-Mauchly (1984) award		dataflow computers, stream processors dblp
Alvin M. Despain	Professor U of Southern California isi.edu/acal/people/despain.html		computer architecture, multiprocessor systems, logic programming, quantum computation, design automation dblp
Dave Detlefs	Sun Labs East research.sun.com/people/detlefs		Extended Static Checker, Simplify theorem prover, garbage collection dblp
Srinivas Devadas	Professor MIT glenfiddich.lcs.mit.edu/~devadas		VLSI design, CAD, computer architecture, hardware validation, architectural synthesis for programmable processors, smart caches, security problems in pervasive computing dblp
Keith Diefendorff	Apple		Apple/PowerPC, AMD K6, Motorola 88110 dblp
Oliver Frank Diessel	Lecturer U of New South Wales, Sydney, Australia cse.unsw.edu.au/~odiessel		design and management of reconfigurable computer systems and applications dblp
Henry G. (Hank) Dietz	Professor U of Kentucky aggregate.org/hankd		parallel processing, compilers, hardware architectures and networking, operating systems, digital imaging dblp
Edsger Wybe Dijkstra	(deceased) U of Texas, Austin, CS cs.utexas.edu/users/UTCS/report/1997/dijkstra.html Turing (1972) award		formal methods dblp
David L. Dill	Professor Stanford U verify.stanford.edu/dill		hardware verification dblp
Chen Ding	Professor U of Rochester, CS cs.rochester.edu/u/cding		compiler enhancement of global cache reuse, dynamic program analysis and transformation, Smooth, performance tuning and prediction for memory hierarchy dblp
Pedro Diniz	Professor U of Southern California Information Sciences Institute isi.edu/~pedro		commutativity analysis, parallelizing compilers, program analysis, parallel and distributed computing, configurable computing dblp
Stephen W. Director	Dean, College of Engineering U of Michigan engin.umich.edu/director		design process, statistical VLSI design dblp
David R. Ditzel	CTO Transmeta Corp.		SPARC, Transmeta dblp
Amer Diwan	Professor U of Colorado, Boulder, CS cs.colorado.edu/~diwan		compiler analyses and optimizations, memory management, memory system performance, power-aware computing, software engineering/visualization tools dblp
Alex Doboli	Professor State U of New York at Stony Brook ece.sunysb.edu/~adoboli		CAD for embedded systems and Systems-on-Chip, specification/modeling/synthesis of heterogeneous-domain systems dblp
Apostolos Dollas	Professor Technical U of Crete mhl.tuc.gr/PERSONEL/cvs/Dollas_alt2.html		rapid system prototyping, computer architecture, reconfigurable computing, embedded systems, application specific high-performance digital systems dblp
Lorenzo Donatiello	Professor U of Bologna, Italy cs.unibo.it/~donat		performance models of computer and communication systems, performability models of fault-tolerant systems, wireless networks, parallel and distributed simulation dblp
Jack Dongarra	Professor U of Tennessee netlib.org/utk/people/JackDongarra		numerical algorithms in linear algebra, parallel computing, use of advanced-computer architectures, programming methodology and tools for parallel computers, LINPACK, MPI, PVM, ScaLAPACK dblp
José Duato	Professor Technical U of Valencia, Spain gap.upv.es/people/jduato/english.html		multicomputer systems, interconnection networks, parallel algorithms, simulation dblp
Pradeep Dubey	Intel Research intel.com/research/people/bios/dubey_p.htm		Altivec, 80386/80486/Pentium, computer architecture, multithreading, multimedia processing dblp
Michel Dubois	Professor U of Southern California, EE usc.edu/dept/ceng/dubois/dubois.html		multiprocessor architecture/performance/algorithms, rapid prototyping engine for multiprocessors (RPM) dblp
Evelyn Duesterwald	IBM		interprocedural data flow analyses