Researchers in Computer Architecture and Compilers

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Name	Address	Picture	Work
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Martín Abadi	Professor U of California at Santa Cruz cse.ucsc.edu/~abadi/home.html	JPEG 81x93 81x93	security, programming languages, specification and verification dblp
Tarek S. Abdelrahman	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~tsa	JPEG 121x176 121x176	Jasmine compiler, NUMAchine multiprocessor, POW system dblp
Mokhtar Aboelaze	Professor York U, Canada cs.yorku.ca/~aboelaze	JPEG 112x140 112x140	omputer networks, mobile networks, computer architecture, special purpose architecture for image processing dblp
Jacob A. Abraham	Professor U of Texas, Austin, ECE cerc.utexas.edu/~jaa	JPEG 80x100 80x100	VLSI design and test, formal verification, fault-tolerant computing dblp
Santosh G. Abraham	Sun Microsystems trimaran.org/car_group/santosh_abraham.html (old)	GIF 100x130 100x130	multiprocessor systems, optimizing compilers, performance evaluation, memory hierarchy simulation and design, Cheetah cache simulator, Trimaran, Elcor dblp
Miron Abramovici	Chief Technical Officer DAFCA Inc. bell-labs.com/user/miron (old)	GIF 137x165 137x165	CAD and testing, reconfigurable computing, FPGAs dblp
David Abramson	Professor Monash U, Australia csse.monash.edu.au/~davida	GIF 128x186 128x186	high performance computer systems design, software engineering tools for programming parallel and distributed supercomputers dblp
Shail (Gupta) Aditya	Senior Research Scientist Hewlett-Packard Labs, Compiler and Architecture Group trimaran.org/car_group/shail_aditya.html	GIF 99x119 99x119	PICO, Elcor, Id, parallel Haskell, parallel computing, compilers dblp
Ali-Reza Adl-Tabatabai	Intel MRL www-2.cs.cmu.edu/~ali	GIF 208x300 208x300	compiler optimizations, debugging dblp
Sarita Adve	Professor U of Illinois Urbana-Champaign, CS rsim.cs.uiuc.edu/~sadve	GIF 102x136 102x136	RSIM, memory consistency models dblp
Vikram S. Adve	Professor U of Illinois Urbana-Champaign, CS www-sal.cs.uiuc.edu/~vadve	GIF 140x166 140x166	link- and run-time compilation, POEMS, dHPF, compilers for distributed applications, LLVM dblp
Anant Agarwal	Professor MIT cag.lcs.mit.edu/~agarwal Maurice Wilkes (2001) award	JPEG 252x320 252x320	RAW, Alewife, Virtual Wires dblp
Gul Agha	Professor U of Illinois at Urbana-Champaign, CS www-osl.cs.uiuc.edu/people?user=agha	JPEG 89x114 89x114	Actors, concurrent programming, formal verification, software engineering, programming languages dblp
Dharma P. Agrawal	Professor U of Cincinnati ececs.uc.edu/~dpa	JPEG 329x460 329x460	ad hoc and sensor networks, wireless and mobile networks, scheduling and task migration on NOWs, multithreaded execution of OO programs, parallelization of irregular FORTRAN loops dblp
Vishwani D. Agrawal	Professor Auburn U eng.auburn.edu/~vagrawal	JPEG 386x474 386x474	SOC test, low-power VLSI design dblp
Alfred V. Aho	Professor Columbia U, CS cs.columbia.edu/~aho	JPEG 157x198 157x198	compilers, AWK dblp
Alexander Aiken	Professor Stanford U, CS theory.stanford.edu/~aiken	GIF 118x158 118x158	type systems, static program analysis and abstract interpretation, constraint resolution algorithms, parallel programming, language design, domain specific languages, end user programming, visualization dblp
Anastassia Ailamaki	Professor Carnegie Mellon U, CS cs.cmu.edu/~natassa	JPEG 107x140 107x140	computer architecture, databases dblp
David Al-Dabass	Professor Nottingham Trent U, UK ducati.doc.ntu.ac.uk/uksim/dad/webpage.htm	JPEG 97x120 97x120	parallel and neural processing, clusters, parallel performance estimation dblp
David H. Albonesi	Professor Cornell U, ECE csl.cornell.edu/~albonesi	GIF 166x256 166x256	computer architecture, microprocessor design, power-aware microarchitecture, performance evaluation dblp
Nikitas A. Alexandridis	Professor George Washington U seas.gwu.edu/~alexan	GIF 80x110 80x110	advanced computer system architectures, high performance processors, parallel and distributed processing, computer vision and image processing/transmission, software prototyping for parallel systems & algorithms, heterogeneous computing dblp
Virgílio A. F. Almeida	Professor U Federal de Minas Gerais, Brazil dcc.ufmg.br/~virgilio	JPEG 107x148 107x148	computing systems performance analysis and modeling, e-commerce dblp
Bowen Alpern	IBM T. J. Watson	?	Jalapeno (Java VM), SSA, theoretical models of hierarchical memory and parallelism, distributed and parallel computing, computational linear algebra dblp
Erik R. Altman	IBM T. J. Watson	?	DAISY, binary translation, software pipelining dblp
Rajeev Alur	Professor U of Pennsylvania cis.upenn.edu/~alur	JPEG 268x376 268x376	design tools for embedded software, formal modeling and verification of reactive systems, model checking, hybrid systems, distributed computing, logic and automata theory dblp
Saman P. Amarasinghe	Professor MIT cag.lcs.mit.edu/~saman	JPEG 125x192 125x192	compiler optimizations, computer architectures, software engineering, parallel computing dblp
Gene M. Amdahl	Retired chairman Commercial Data Servers Inc actscorp.com/acts/amdahl.htm Eckert-Mauchly (1987) award	JPEG 99x112 99x112	pipelining, instruction look-ahead, cache dblp
Henrik Reif Andersen	Professor IT University of Copenhagen, Denmark itu.dk/people/hra	JPEG 539x779 539x779	verification of concurrent and embedded systems, model checking, modal mu-calculus, models of concurrent systems, configuration problems and configuration software, implementation of embedded systems dblp
Tom Anderson	Professor U of Washington Seattle, CS cs.washington.edu/homes/tom	JPEG 115x131 115x131	Internet, operating systems, scheduler activations dblp
David Andrews	Professor U of Kansas ittc.ku.edu/~dandrews	JPEG 115x156 115x156	real time distributed, embedded systems, computer architecture dblp
Andrew W. Appel	Professor Princeton U cs.princeton.edu/~appel	GIF 114x151 114x151	compilers, functional programming languages dblp
James R. Armstrong	Professor Virginia Tech, EE ecpe.vt.edu/faculty/armstrong.html	GIF 84x104 84x104	modeling with hardware description languages, high level testing dblp
Mark G. Arnold	Professor Lehigh U cse.lehigh.edu/~marnold	JPEG 68x93 68x93	computer architecture and arithmetic, hardware description languages dblp
Arvind	Professor MIT csg.lcs.mit.edu/Users/arvind	GIF 76x95 76x95	term-rewriting systems, dynamic dataflow, Id dblp
Krste Asanovic	Professor MIT cag.lcs.mit.edu/~krste	JPEG 138x174 138x174	T0 vector microprocessor, low power, neural network implementations dblp
John Vincent Atanasoff	Professor (deceased) Iowa State U, CS cs.iastate.edu/jva/jva-archive.shtml	GIF 136x151 136x151	first digital computer
Peter M. Athanas	Professor Virginia Tech, EE ee.vt.edu/~athanas	GIF 82x95 82x95	computer architecture, VLSI, custom computing machines, parallel processing, hardware/software codesign, high-level synthesis, rapid prototyping of digital systems dblp
Darren C. Atkinson	Professor Santa Clara U cse.scu.edu/~atkinson	JPEG 67x80 67x80	software engineering, compilers dblp
David I. August	Professor Princeton U, CS cs.princeton.edu/~august	JPEG 96x129 96x129	compilers for predicated architectures dblp
Todd M. Austin	Professor U of Michigan eecs.umich.edu/~taustin	JPEG 150x192 150x192	SimpleScalar, Diva (Dynamic Verification), microarchitecture design, low power computing, compiler design, computer system simulation and validation, performance analysis tools and techniques dblp
Eduard Ayguade	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/eduard	JPEG 83x125 83x125	parallelizing compilers, OpenMP, data placement optimization, parallel computing in Java, ILP dblp
James H. Aylor	Professor U of Virginia, EE ee.virginia.edu/profile.php?ID=2	PNG 91x116 91x116	system-level modeling, concurrent error detection, automatic test pattern generation, hardware description languages, VLSI system design dblp
Adnan Aziz	Professor U of Texas, Austin, ECE ece.utexas.edu/~adnan	JPEG 112x147 112x147	design and verification of digital IC dblp
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Bevan M. Baas	Professor UC Davis ECE ece.ucdavis.edu/~bbaas/	JPEG 117x158 117x158	processor architecture, VLSI design, fast Fourier transform processors, low power CMOS
John Backus	computerhistory.org/events/hall_of_fellows/backus/ Turing (1977) award	GIF 128x159 128x159	FORTRAN, Backus-Naur form dblp
David F. Bacon	Researcher IBM T. J. Watson research.ibm.com/people/d/dfb/	JPEG 90x116 90x116	design and implementation of programming languages, concurrent systems dblp
Wael M. Badawy	Professor U of Calgary, Canada badawy.ca	JPEG 294x370 294x370	architectures for image and video processing, system on a chip dblp
Scott B. Baden	Professor UC San Diego, CS cs.ucsd.edu/users/baden	JPEG 220x334 220x334	high performance and scientific computation, application-specific programming models and optimization strategies, KeLP dblp
Jean-Loup Baer	Professor U of Washington Seattle, CS cs.washington.edu/homes/baer	JPEG 711x786 711x786	caches, computer architecture, programmable network interfaces dblp
Nader Bagherzadeh	Professor UC Irvine eng.uci.edu/comp.arch/nader.html	GIF 104x127 104x127	MorphoSys, multithreaded architectures, processor architecture dblp
R. Iris Bahar	Professor Brown U, ECE lems.brown.edu/iris.html	GIF 167x197 167x197	computer architecture, low-power design, CAD, nanosystem design dblp
Vasanth Bala	IBM research	?	parallel computation, Dynamo, dynamic optimization dblp
Thomas Ball	Microsoft Research, Software Productivity Tools research.microsoft.com/~tball	JPEG 75x75 75x75	formal methods for programs dblp
Prithviraj Banerjee	Professor Northwestern U, ECE ece.nwu.edu/~banerjee	JPEG 236x317 236x317	parallel algorithms for VLSI design automation, distributed memory parallel compilers, compilers for adaptive computing, PARADIGM, ProperCAD, MATCH dblp
Cristina Barrado	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/cristina	?	automatic parallelization dblp
Luiz André Barroso	Google barroso.org	JPEG 120x160 120x160	server workloads, SimOS-Alpha dblp
Rajeev Barua	Professor U of Maryland, ECE ece.umd.edu/~barua	GIF 291x359 291x359	MAPS (Raw compiler), modulo unrolling dblp
Forest Baskett	Venture Partner New Enterprise Associates nea.com/Partners/Bios/Menlo/FBaskettBio	JPEG 109x142 109x142	MIPS, SUN, DEC WRL founder dblp
Kenneth E. Batcher	Professor Kent State U, CS cs.kent.edu/~batcher Eckert-Mauchly (1990) award	GIF 120x141 120x141	parallel computers, interconnection networks dblp
Jürgen Becker	Professor U of Karslruhe www-itiv.etec.uni-karlsruhe.de/opencms/opencms/de/institute/staff/becker.html	JPEG 70x70 70x70	hardware/software codesign, hardware synthesis, systems-on-a-chip dblp
Robert C. Bedichek	Transmeta Corp. bedichek.org/robert	JPEG 187x263 187x263	Alewife, Meerkat, multicomputers dblp
Peter A. Beerel	Professor U of Southern California jungfrau.usc.edu/beerel.html	JPEG 224x303 224x303	CAD, mixed asynchronous/synchronous VLSI design dblp
Richard A. Belgard	Consultant members.aol.com/richb89600	GIF 99x139 99x139	computer architecture
Gordon Bell	senior researcher Microsoft Bay Area Research Center research.microsoft.com/users/GBell Eckert-Mauchly (1982) award	GIF 111x125 111x125	minicomputers, timeshring, hardware description languages dblp
Luca Benini	Professor U of Bologna, Italy www-micrel.deis.unibo.it/~benini	JPEG 89x111 89x111	computer-aided design of digital circuits, low-power applications, design of portable systems dblp
Siegfried Benkner	Professor U of Vienna, Austria par.univie.ac.at/~sigi	JPEG 304x355 304x355	ADVANCE, AURORA, HPF+ dblp
Steve Bennett	Intel, Hillsboro intel.com/research/people/bios/bennett_s.htm	?	SimpleScalar, trace cache, multiscalar dblp
Alan D. Berenbaum	Agere Systems cm.bell-labs.com/cm/cs/who/adb	GIF 107x129 107x129	computer architecture, architectural support for high-speed networking, VLSI design dblp
Emery D. Berger	Professor U of Massachusetts Amherst, CS cs.umass.edu/~emery	JPEG 101x136 101x136	garbage collection, virtual memory management, locality-preserving data structures, compilers for high-level optimization and error detection dblp
Neil W. Bergmann	Professor U of Queensland, Brisbane, Australia itee.uq.edu.au/~bergmann	JPEG 92x117 92x117	reconfigurable computing, embedded systems infrastructure for ubiquitous computing dblp
Kees van Berkel	Philips Research, Netherlands research.philips.com/profile/people/fellows/berkel.html	JPEG 73x97 73x97	asynchronous circuits, VLSI design dblp
David Bernstein	Department Manager Systems and Software, IBM Research Israel	?	code scheduling, optimizing compilers dblp
Gerard Berry	Professor Ecole des Mines, Paris, France www-sop.inria.fr/meije/personnel/Gerard.Berry.html	JPEG 201x257 201x257	programming languages design/semantics/implementation, reactive and real-time programming, synchronous circuit design and synthesis, automatic verification of FSM, lambda calculus and its models dblp
Vaughn Betz	Altera Corp. eecg.toronto.edu/~vaughn (old)	JPEG 100x142 100x142	FPGAs, CAD for FPGAS, computer architecture, VLSI design, VPR dblp
Dileep Bhandarkar	Director of Enterprise Architecture Lab Intel intel.com/pressroom/kits/bios/dbhandarkar.htm	JPEG 122x163 122x163	VAX, Prism, MIPS, Alpha, memories, computer architecture dblp
Shuvra S. Bhattacharyya	Professor U of Maryland, ECE ece.umd.edu/~ssb	JPEG 133x156 133x156	architectures and CAD for embedded systems, hardware/software co-design for signal/image/video processing dblp
Laxmi N. Bhuyan	Professor UC Riverside, CS cs.ucr.edu/~bhuyan	JPEG 106x143 106x143	computer architecture, performance evaluation, parallel and distributed systems, interconnection networks, fault tolerant computing dblp
Ricardo Bianchini	Professor Rutgers U, CS cs.rutgers.edu/~ricardob	JPEG 59x75 59x75	parallel/distributed and cluster computing, techniques for optimizing power and energy, new I/O architectures, Internet-related technologies dblp
Armin Biere	Professor ETH Zurich, Switzerland inf.ethz.ch/personal/biere	GIF 121x149 121x149	model checking, hardware verification dblp
Aart J. C. Bik	Intel liacs.nl/home/ajcbik	JPEG 138x159 138x159	compilers for scientific computing, Java compilation, automatic vectorization dblp
Angelos Bilas	Professor U of Crete, Greece wwww.ics.forth.gr/~bilas	GIF 71x100 71x100	parallel architectures, programming paradigms, parallel applications, interconnection networks, block-level storage subsystems, performance analysis and evaluation, distributed systems dblp
Benjamin J. Bishop	Professor U of Scranton, CS cs.uofs.edu/~bishop	JPEG 129x175 129x175	multimedia systems, computer graphics, processor architecture, VLSI design, low-power electronics, MGAP-II, SPARTA dblp
David T. Blaauw	Professor U of Michigan at Ann Arbor eecs.umich.edu/cgi-bin/fac/facsearchform.cgi?blaauw+	JPEG 81x105 81x105	circuit analysis, computer-aided design, high performance design dblp
Stephen M. Blackburn	Professor Australian National U, Australia cs.anu.edu.au/~Steve.Blackburn	JPEG 126x177 126x177	programming languages, dynamic cooperative performance optimization Java, transactional object storage, image processing dblp
R. D. (Shawn) Blanton	Professor Carnegie Mellon U, ECE ece.cmu.edu/~blanton	GIF 71x91 71x91	design and test of VLSI, fault-tolerant computing, computer architecture dblp
Guy E. Blelloch	Professor Carnegie Mellon U, CS cs.cmu.edu/~guyb	GIF 192x256 192x256	thread scheduling, parallel algorithms, NESL language, parallel computing dblp
Matthias Blume	Professor Toyota Technical Institute, Chicago people.cs.uchicago.edu/~blume	GIF 128x167 128x167	design and implementation of high-level programming languages, SML/NJ dblp
Matthias A. Blumrich	IBM Research cs.princeton.edu/~mb (old)	GIF 71x88 71x88	SHRIMP, shared memory multiprocessing dblp
Arndt Bode	Professor Technische U Muenchen, Germany wwwbode.cs.tum.edu/~bode	JPEG 161x203 161x203	parallel and distributed architectures/applications, programming environments and tools dblp
Rastislav Bodík	Professor UC Berkeley cs.berkeley.edu/~bodik	GIF 89x124 89x124	critical path, compilers, computer architecture dblp
François Bodin	Researcher IRISA, France irisa.fr/caps/people/bodin/index_fr.htm	GIF 274x316 274x316	program optimizations, HPC programming environments, compilers, ILP, parallel computers dblp
Hans-Juergen Boehm	Hewlett-Packard Labs hpl.hp.com/personal/Hans_Boehm/	JPEG 144x181 144x181	Boehm-Weiser garbage collector, gcj, multiprocessor synchronization, constructive real arithmetic dblp
Taisuke Boku	Professor U of Tsukuba, Japan arch.is.tsukuba.ac.jp/~taisuke/index-e.html	GIF 83x102 83x102	network topology, data transfer methods for HPC on MPPs dblp
Shekhar Y. Borkar	Director of Circuit Research Intel intel.com/research/people/bios/borkar_s.htm	JPEG 83x106 83x106	8051 microcontrollers, iWarp, high-speed signaling for supercomputers dblp
Pradip Bose	Research Staff Member IBM T. J. Watson research.ibm.com/people/b/bose	JPEG 309x374 309x374	high-performance computer architectures, CAD, performance evaluation, performance verification, parallel processing, compilers, VLSI testing and verification dblp
Luc Bougé	Professor IRISA/ENS Cachan, Bretagne, France ens-lyon.fr/~bouge	JPEG 76x82 76x82	semantics of languages for parallel programming, cluster computing dblp
Donald W. Bouldin	Professor U of Tennessee at Knoxville microsys6.engr.utk.edu/ece/bouldin_home.html	GIF 109x132 109x132	microelectronic systems design, adaptive computing systems, VLSI, ASICs, FPGAs, MCMs, synthesis dblp
Chandrasekhar Boyapati	Professor U of Michigan eecs.umich.edu/~bchandra	JPEG 346x512 346x512	software reliability, program analysis dblp
Robert S. Boyer	Professor U of Texas, Austin, CS cs.utexas.edu/users/boyer	JPEG 55x77 55x77	theorem prooving, Maxima (Macsyma clone), Boyer-Moore theorem prover, hardware verification dblp
Robert K. Brayton	Professor UC Berkeley, EE www-cad.eecs.berkeley.edu/~brayton	GIF 216x258 216x258	analysis of nonlinear networks, electrical simulation and optimization of circuits, combinational and sequential logic synthesis, asynchronous synthesis, formal verification dblp
Scott E. Breach	Hewlett-Packard cs.wisc.edu/~breach (old)	JPEG 147x178 147x178	multiscalar processors dblp
Gordon J. Brebner	Professor U of Edinburgh, UK dcs.ed.ac.uk/home/gordon	GIF 92x127 92x127	flexible architecture and networking dblp
Mauricio Breternitz Jr.	Intel MRL intel.com/research/people/bios/breternitz_m.htm	?	parallelizing compilers multiprocessors and VLIW, binary translation, on IP telephony, parallelizing database servers dblp
Melvin A. Breuer	Professor U of Southern California poisson.usc.edu/Breuer.html	GIF 100x131 100x131	CAD, design-for-test and built-in self-test, VLSI circuits dblp
Faye A. Briggs	director of chipset architecture Intel Enterprise Products Group	JPEG 154x168 154x168	computer architecture, parallel processing dblp
Robert W. Brodersen	Professor UC Berkeley, ECE bwrc.eecs.berkeley.edu/People/Faculty/rb	JPEG 565x750 565x750	low power design, wireless communications, CAD tools dblp
Stephen D. Brookes	Professor Carnegie Mellon U, CS csd.cs.cmu.edu/research/faculty_research/brookes.html	JPEG 48x64 48x64	semantics of programming languages, trace semantics dblp
David Brooks	Professor Harvard U eecs.harvard.edu/~dbrooks	?	interaction architecture/software/hardware, power dissipation and chip cooling modelling, Wattch dblp
Frederick P. Brooks Jr.	Professor U of North Carolina, CS cs.unc.edu/~brooks Turing (1999) award, von Neumann medal (1993), National Medal of Technology (1985), Allen Newell (1994) award, Eckert-Mauchly (2004) award	JPEG 89x101 89x101	3D interactive computer graphics, human-computer interaction, virtual worlds, molecular graphics, IBM S/360, STRETCH, The Mythical Man-Month dblp
Mats Brorsson	Professor Royal Institute of Technology, Stockholm, Sweden it.kth.se/~matsbror	GIF 237x324 237x324	energy aware architectures, shared address space multiprocessors, programming models for parallel programs, software DSM dblp
Angela Demke Brown	Professor U of Toronto, CS, Canada cs.toronto.edu/~demke	JPEG 70x84 70x84	compiler-guided resource management, run-time adaptation, operating systems, compiler optimization, parallel and distributed systems dblp
Donna J. Brown	Professor U of Illinois at Urbana-Champaign, ECE wocket.csl.uiuc.edu/~djb	JPEG 87x100 87x100	VLSI layout, combinatorial algorithms, parallel and distributed algorithms and architecture, Web-based instruction, Mallard dblp
Richard B. Brown	Dean, College of Engineering U of Utah coe.utah.edu/brown	JPEG 318x373 318x373	IC design (VLSI), solid-state chemical sensors, MEMS, mixed-signal circuits, high-performance, radiation-hard and low-power microprocessors, CMOS/SOI/GaAs dblp
Stephen Dean Brown	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~brown	GIF 157x206 157x206	FPGAs, CAD, place and route dblp
Erik Brunvand	Professor U of Utah, CS cs.utah.edu/~elb/home.html	JPEG 91x98 91x98	computer architecture, VLSI systems, self-timed and asynchronous systems dblp
Randal E. Bryant	Professor Carnegie Mellon U, CS cs.cmu.edu/~bryant	GIF 123x169 123x169	Binary Decision Diagrams (BDD), formal verification, model checking dblp
Mihai Budiu	Microsoft Research cs.cmu.edu/~mihaib (old)	JPEG 233x276 233x276	reconfigurable hardware, optimizing compilers, spatial computation dblp
Duncan A. Buell	Professor U of South Carolina cse.sc.edu/~buell	JPEG 953x1337 953x1337	Splash 2 reconfigurable system, numeric computations, parallel algorithms and architectures, computational number theory dblp
Doug Burger	Professor U of Texas, Austin, CS cs.utexas.edu/users/dburger	JPEG 185x243 185x243	SimpleScalar, Datascalar, memory systems dblp
Neil Burgess	Professor Cardiff U, UK engin.cf.ac.uk/whoswho/profile.asp?RecordNo=138	JPEG 72x91 72x91	computer arithmetic, digital signal processing, hardware support for DSP dblp
Wayne P. Burleson	Professor U of Massachusetts Amherst ECE ecs.umass.edu/ece/vspgroup/burleson.html	GIF 116x147 116x147	VLSI signal processing, on-chip interconnects, reconfigurable computing dblp
Martin Burtscher	Professor Cornell U, ECE csl.cornell.edu/~burtscher	GIF 75x87 75x87	high-performance microprocessor architecture, ILP, compiler optimizations, value prediction, data compression, latency-reduction techniques dblp
Rajkumar Buyya	Professor Monash U, Australia buyya.com	JPEG 96x121 96x121	computer architecture, operating systems, compilers, parallel / distributed / cluster / grid / peer-to-peer computing dblp
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George Z. N. Cai	Engineering manager Intel Design Center, Texas	?	power modeling and management, microprocessor design and implementation dblp
Brad Calder	Professor UC San Diego www-cse.ucsd.edu/users/calder	JPEG 87x122 87x122	prediction, mobile code, PSSA dblp
Timothy J. Callahan	post-doc Carnegie Mellon U, CS www-2.cs.cmu.edu/~tcal	JPEG 70x83 70x83	GARP, reconfigurable hardware compilation, system-on-a-chip design automation, hardware/software codesign dblp
João M. P. Cardoso	Professor U of Algarve, Portugal w3.ualg.pt/~jmcardo	JPEG 549x659 549x659	reconfigurable computing, high-level synthesis for FPGAs, design automation for embedded systems dblp
Douglas M. Carmean	principal engineer/architect Intel Desktop Products, Oregon	GIF 61x89 61x89	IA-32, Pentium, Pentium 4 dblp
Steven M. Carr	Professor Michigan Technological U, CS cs.mtu.edu/~carr	GIF 69x86 69x86	high-level optimization for DSP, compilers-computer architecture interaction, concurrent computing dblp
John B. Carter	Professor U of Utah, CS cs.utah.edu/~retrac	GIF 208x263 208x263	operating systems, parallel and distributed computing, multiprocessor computer architecture, memory system design, Munin dblp
Lori Carter	Professor Point Loma Nazarene U, San Diego mcs.ptloma.edu/Carter	JPEG 197x185 197x185	computer architecture, compiler optimizations, predicated execution, compilation for IA64 dblp
Nicholas P. Carter	Professor U of Illinois Urbana-Champaign, ECE crhc.uiuc.edu/~npcarter	JPEG 113x152 113x152	reconfigurable logic, computing using non-silicon dblp
Calin Cascaval	IBM T. J. Watson polaris.cs.uiuc.edu/~cascaval (old)	JPEG 122x169 122x169	parallel compilers, parallel and distributed computing, object oriented compilers and methodologies dblp
Steve Casselman	Virtual Computer Corp	?	reconfigurable computing, search engines dblp
Gregory J. Chaitin	IBM T. J. Watson cs.umaine.edu/~chaitin	JPEG 150x179 150x179	register allocation, algorithmic information theory dblp
Craig Chambers	Professor U of Washington Seattle, CS cs.washington.edu/homes/chambers	JPEG 70x96 70x96	SPIN, dynamic compilation, Vortex, Cecil dblp
Fay Chang	Google cs.cmu.edu/~fwc (old)	?	Speculative prefetching for disk data, distributed filesystems dblp
J. Morris Chang	Professor Iowa State U, EE vulcan.ee.iastate.edu/~morris	JPEG 183x207 183x207	wireless network, computer architecture, object-oriented programming languages, memory management, hardware description languages, internet architecture dblp
Craig M. Chase	Professor U of Texas, Austin, ECE ece.utexas.edu/~chase	JPEG 80x100 80x100	parallel architectures and algorithms dblp
Siddhartha Chatterjee	Professor U of North Carolina, CS cs.unc.edu/~sc	JPEG 121x153 121x153	cache-conscious algorithms, data parallelism dblp
Tiberiu Chelcea	postdoc Carnegie Mellon U, CS cs.cmu.edu/~tibi	JPEG 78x91 78x91	asynchronous circuits dblp
Peter M. Chen	Professor U of Michigan eecs.umich.edu/~pmchen	JPEG 285x402 285x402	RIO, ARMADA, fault tolerance, disk systems dblp
Tien-Fu Chen	Professor National Chung Cheng U, China cs.ccu.edu.tw/~chen	GIF 186x202 186x202	computer architecture, SOC design, embedded systems dblp
Fu-Chiung John Cheng	Professor Tatung U, Taiwan cse.ttu.edu.tw/~cheng	JPEG 94x116 94x116	Systems-on-a-chip, hardware-software codesign, CAD tools, asynchronous logic, FPGAs, Java-enabled embedded systems, real-time OS, expert database systems dblp
Perry Cheng	IBM T.J. Watson research.ibm.com/people/p/perryche	JPEG 152x168 152x168	garbage collection, type-directed compilation dblp
David R. Cheriton	Professor Stanford U www-dsg.stanford.edu/DavidCheriton.html	GIF 64x86 64x86	distributed systems, high performance networks, operating systems, distributed interactive simulation, object-oriented design techniques dblp
Peter Y. K. Cheung	Professor Imperial College, London, UK ee.ic.ac.uk/pcheung	JPEG 100x113 100x113	reconfigurable computing, hardware/software codesign, CAD, Digital and Asynchronous Systems, VLSI architecture for signal processing, mixed signal designs dblp
Men-Chow Chiang	IBM Server Group	?	memory systems for multiprocessors dblp
Donald M. Chiarulli	Professor U of Pittsburgh, EE cs.pitt.edu/~don	JPEG 94x141 94x141	chip level optoelectronic interconnections, optical-electronic-mechanical multi-domain CAD, optical memory systems, robotics, SOC voice based interfaces dblp
Andrew A. Chien	Professor UC San Diego www-csag.ucsd.edu/individual/achien/achien.html	GIF 120x140 120x140	Agile Distributed Objects, High Performance Virtual Machines (HPVM), Illinois Concert Project, QoS management dblp
Bruce R. Childers	Professor U of Pittsburgh, CS cs.pitt.edu/~childers	JPEG 64x77 64x77	automatic design of application-specific processors, custom VLIW/systolic architectures, low-power embedded processors, computer architecture, compilers and software development tools dblp
Trishul M. Chilimbi	Microsoft Research research.microsoft.com/~trishulc	GIF 97x123 97x123	optimizations for caching dblp
Giovanni Chiola	Professor U di Genova, Italy disi.unige.it/person/ChiolaG	JPEG 122x192 122x192	active messages (GAMMA), distributed databases dblp
Derek Chiou	Professor U of Texas at Austin ECE ece.utexas.edu/~derek	JPEG 104x142 104x142	simulators, sequential and parallel computer architectures, router architecture, dataflow machines, StarT dblp
Jong-Deok Choi	IBM Research T. J. Watson research.ibm.com/people/j/jdchoi	?	programming languages, compiler optimizations, software engineering dblp
Kiyoung Choi	Professor Seoul National U, Korea poppy.snu.ac.kr/~kchoi/kchoi.html	JPEG 85x103 85x103	VLSI design, CAD, hardware-software codesign, high-level synthesis, low-power system design dblp
Frederic T. Chong	Professor UC Davis, CS american.cs.ucdavis.edu:80/~chong	GIF 148x159 148x159	Active Pages dblp
Pai H. Chou	Professor UC Irvine ece.uci.edu/~chou	JPEG 78x91 78x91	IMPACCT, embedded systems, low power design dblp
Alok N. Choudhary	Professor Northwestern U ECE ece.northwestern.edu/~choudhar	GIF 119x156 119x156	compilers and runtime systems for high-performance embedded/adaptive/power-aware systems, high-performance databases, parallel and high-performance storage and I/O systems dblp
Fred C. Chow	Pathscale, Inc.	?	optimizing compilers dblp
Paul Chow	Professor U of Toronto, EE, Canada eecg.toronto.edu/~pc	GIF 85x103 85x103	FPGAs, OneChip, Transmogrifier-2 dblp
Giuseppe Ciaccio	Professor U di Genova, Italy disi.unige.it/person/CiaccioG	JPEG 133x133 133x133	clusters of PCs, operating systems, parallel processing, parallel computer architecture dblp
Michal Cierniak	researcher Intel Microprocessor Research Labs, Programming Systems Lab intel.com/research/mrl/people/cierniak_m.htm	GIF 88x105 88x105	virtual machines, runtime systems, just-in-time compilation, high-performance compiler optimizations dblp
Marcelo H. Cintra	Professor U of Edinburgh, UK dcs.ed.ac.uk/home/mc	JPEG 72x99 72x99	computer architectures, parallel and high-performance computing, scientific computing dblp
Douglas W. Clark	Professor Princeton U, CS cs.princeton.edu/~doug	GIF 83x112 83x112	processor architecture and organization, performance measurement and analysis, computer architecture, Display Wall dblp
Wesley A. Clark	Clark, Rockoff and Associates Eckert-Mauchly (1981) award	JPEG 127x170 127x170	design of early computers, TX-0, TX-2 dblp
Edmund M. Clarke	Professor Carnegie Mellon U, CS cs.cmu.edu/~emc	GIF 85x117 85x117	formal verification, model checking dblp
John G. Cleary	Professor U of Waikato, New Zealand cs.waikato.ac.nz/Staff/john-g.-cleary.html	JPEG 202x233 202x233	parallel and distributed systems, TimeWarp, compression, logic programming dblp
Cliff Click	Motorola crpc.rice.edu/MSCP/cliff.html (old)	GIF 72x89 72x89	compiler optimizations, intermediate program representations dblp
John Cocke	(deceased) IBM T. J. Watson Eckert-Mauchly (1985) award, Turing (1987) award	GIF 168x190 168x190	optimizing compilers, RISC processors dblp
Robert S. Cohn	Intel	GIF 69x80 69x80	Alpha compilers, profile-feedback compilation, Spike, code layout in Unix OM dblp
Michele Colajanni	Professor U di Modena, Italy traianus.ce.uniroma2.it/people/colajanni.html	JPEG 80x110 80x110	distributed parallel computing, distributed web servers, parallel scientific computing, fault-tolerance, interconnection networks, performance analysis and simulation dblp
Osvaldo Colavin	ST Microelectronics	?	architectural support for multimedia dblp
Jean-Francois Collard	Intel prism.uvsq.fr/~jfcollar (old)	JPEG 112x156 112x156	automatic parallelization, optimizing compilers dblp
Robert P. Colwell	Colwell and Associates, Inc. Eckert-Mauchly (2005) award	GIF 56x66 56x66	Pentium Pro, Multiflow dblp
Hubert Comon-Lundh	Professeur Ecole Normale Superieure de Cachan, France lsv.ens-cachan.fr/~comon/	JPEG 132x150 132x150	term rewriting, symbolic constraint solving, tree automata techniques, verification of infinite state systems, cryptographic protocols dblp
Katherine Compton	Professor U of Wisconsin-Madison ECE ece.wisc.edu/~kati/	JPEG 150x230 150x230	reconfigurable computing dblp
Jason Cong	Professor U of California at Los Angeles, CS ballade.cs.ucla.edu/~cong	GIF 221x280 221x280	hardware synthesis, giga-scale system-on-a-chip, FPGAs, large-scale CAD dblp
Daniel A. Connors	Professor U of Colorado, CS cs.colorado.edu/~dconnors	JPEG 70x82 70x82	high performance computer systems, run-time optimization architectures, embedded systems, optimizing compilers, operating systems dblp
Charles Consel	Professor ENSEIRB/LaBRI/INRIA Bordeaux, France compose.labri.u-bordeaux.fr/people/consel	GIF 120x148 120x148	programming languages, program analysis and transformation, software engineering, operating systems dblp
Thomas M. Conte	Professor North Carolina State U, ECE tconte.org	JPEG 293x345 293x345	compiler design, advanced microarchitectures, VLIW/IA-64 compilers dblp
Lynn Conway	Professor (emeritus) U of Michigan ai.eecs.umich.edu/people/conway/conway.html	JPEG 119x155 119x155	VLSI, robotics/AI dblp
Stephen A. Cook	Professor U of Toronto, CS, Canada cs.toronto.edu/~sacook Turing (1982) award	JPEG 166x220 166x220	NP-completeness, computational complexity, logic dblp
William R. Cook	Professor U of Texas at Austin, CS cs.utexas.edu/users/wcook	JPEG 164x203 164x203	programming languages, mixins, type theory, object-oriented programming, interfacing languages and databases, software engineering, web-based information systems, information security dblp
Keith D. Cooper	Professor Rice U, CS cs.rice.edu/~keith	GIF 125x147 125x147	Rn, ParaScope, low-level code optimization, code generation, GrDAS dblp
Lee D. Coraor	Professor Penn State U cse.psu.edu/gradbroc/faculty/coraor.html	JPEG 156x217 156x217	FPGAs, SmartDIMM (computing in memory) dblp
Henk Corporaal	Professor Technische U Eindhoven, Netherlands ics.ele.tue.nl/~heco	GIF 166x241 166x241	automatic synthesis of application specific processors, very large scale distributed embedded DSP systems dblp
Jordi Cortadella	Professor U Politecnica de Catalunya, Spain lsi.upc.es/~jordic	JPEG 129x168 129x168	synthesis, analysis and verification of concurrent systems, asynchronous systems, logic synthesis, Petrify dblp
Michel Cosnard	Professor/director INRIA inria.org/presse/cvmc.en.html	JPEG 104x138 104x138	parallel algorithms and architectures, algorithm complexity, automata theory and neural networks, discrete dynamical systems dblp
Patrick Cousot	Professor Ecole Normale Superieure Paris, France di.ens.fr/~cousot	JPEG 156x207 156x207	abstract interpretation, semantics dblp
Radhia Cousot	Research Director Ecole Polytechnique, France di.ens.fr/~cousot	?	abstract interpretation, semantics, proofs dblp
Alan L. Cox	Professor Rice U, CS cs.rice.edu/~alc	JPEG 69x89 69x89	TreadMarks, FASTLINK dblp
Harvey G. Cragon	Professor (emeritus) U of Texas, Austin, ECE ece.utexas.edu/ece/people/profs/Cragon.html Eckert-Mauchly (1986) award	GIF 60x74 60x74	first integrated circuit computer, first TTL computer dblp
Karl Crary	Professor Carnegie Mellon U, CS cs.cmu.edu/~crary	JPEG 279x305 279x305	type-oriented compilation strategies, type-based certification of mobile code, high-level programming language design dblp
John Crawford	Director of McKinley Architecture Intel Architecture Group, Enterprise Platforms Group intel.com/pressroom/kits/bios/crawford.htm Eckert-Mauchly (1995) award	JPEG 119x154 119x154	IA-64, 80386, Pentium dblp
Seymour Cray	(deceased) cgl.ucsf.edu/home/tef/cray/tribute.html Eckert-Mauchly (1989) award	GIF 140x177 140x177	supercomputers
Stefano Crespi-Reghizzi	Professor Politecnico di Milano, Italy elet.polimi.it/people/crespi	JPEG 329x383 329x383	formal languages and automata, compiler optimization and parallelization, programming languages, man-machine interfaces dblp
Darren C. Cronquist	Hewlett-Packard Labs, Compiler and Architecture Group hpl.hp.com/research/itc/car/Templates/darren-cronquist-page.html	JPEG 79x96 79x96	architectures/compilers/languages for embedded applications, RaPiD (reconfigurable hardware), PICO dblp
Mark Crovella	Professor Boston U, CS cs-www.bu.edu/faculty/crovella	GIF 153x210 153x210	performance evaluation of parallel and networked computers, measuring and characterizing the web dblp
David E. Culler	Professor UC Berkeley, CS cs.berkeley.edu/~culler	JPEG 74x85 74x85	Active Messages, Threaded Abstract Machine, parallel architectures dblp
Walling R. Cyre	Professor Virginia Tech, EE ecpe.vt.edu/faculty/cyre.html	JPEG 103x134 103x134	automatic design, requirements analysis, natural language understanding, automatic modeling, high-level synthesis, design representation dblp
Ronald K. Cytron	Professor Washington U in St. Louis, CS cs.wustl.edu/~cytron	JPEG 74x89 74x89	SSA, compilers, continuous compilers, packet filtering, secure voting dblp
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Ole-Johan Dahl	(deceased) Oslo U, Norway ifi.uio.no/~olejohan Turing (2001) award, von Neumann Medal (2001)	JPEG 83x112 83x112	Simula, type theory, object-oriented programming dblp
Fredrik Dahlgren	Professor Chalmers U, Goteborg, Sweden ce.chalmers.se/~dahlgren	JPEG 100x108 100x108	high-performance multiprocessors, multiprocessors for telecom systems dblp
William J. Dally	Professor Stanford U csl.stanford.edu/~billd Maurice Wilkes (2000) award	JPEG 323x389 323x389	Imagine, J-machine, the reliable router, high-speed interconnection networks dblp
Marco Danelutto	Professor U of Pisa, Italy di.unipi.it/~marcod	GIF 208x258 208x258	parallel programming with skeletons, P3L, parallel functional, ocamlp3l, (massively) parallel architectures, ILP, Linux clusters dblp
Alain Darte	Researcher CNRS ens-lyon.fr/~darte/index-us.html	GIF 251x310 251x310	automatic parallelization, HPF, Nestor, scheduling, systolic arrays dblp
Chitaranjan R. Das	Professor Pennsylvania State U cse.psu.edu/~das	GIF 208x255 208x255	computer architecture, parallel and distributed computing, design and analysis of routing algorithms, processor management in multiprocessors, performance evaluation and fault-tolerant computing dblp
Manuvir Das	Microsoft Research research.microsoft.com/users/Manuvir/homepage.html	JPEG 75x75 75x75	static program analysis, application to compilers/error detection/program verification dblp
Aravind Dasu	Professor Utah State U ece.usu.edu/ece/faculty_staff/profile.php?id=229	JPEG 83x121 83x121	reconfigurable computing for media and scientific computing dblp
Edward S. Davidson	Professor (emeritus) U of Michigan eecs.umich.edu/~davidson Eckert-Mauchly (2000) award	GIF 129x153 129x153	computer architecture, supercomputing, parallel and pipelined computers, performance modeling and optimization, application code, assessment and tuning, VLSI systems, memory organization and management, CAD dblp
Jack W. Davidson	Professor U of Virginia, CS cs.virginia.edu/~jwd	JPEG 82x116 82x116	zephyr, high-performance embedded applications, dynamic optimization for power dblp
Al Davis	Professor U of Utah, CS cs.utah.edu/~ald	JPEG 287x365 287x365	parallel computer architecture, adaptive memory systems, asynchronous circuits and systems dblp
Nathaniel J. Davis	Professor Virginia Tech, EE ecpe.vt.edu/faculty/davisnj.html	JPEG 93x115 93x115	advanced computer architectures, parallel processing, interconnection networks, computer networks, computer system simulation and performance modeling, embedded microprocessor systems dblp
Koen De Bosschere	Professor Ghent U, Belgium elis.ugent.be/~kdb	JPEG 160x226 160x226	debugging of parallel programs, Java technology, link-time optimization, computer architecture dblp
Bjorn De Sutter	postdoc Gent U, Belgium elis.ugent.be/~brdsutte	JPEG 420x575 420x575	binary rewriting, embedded software optimization, low-power optimization, reconfigurable computing, software protection techniques, computer architecture, program compaction dblp
Alexander G. Dean	Professor North Carolina State U cesr.ncsu.edu/agdean	JPEG 122x168 122x168	computer architecture and compilation techniques for embedded systems, software thread integration dblp
Saumya K. Debray	Professor U of Arizona cs.arizona.edu/people/debray	JPEG 157x193 157x193	programming languages and compilers, binary rewriting and link-time code optimization, code compression dblp
James C. Dehnert	Transmeta	?	compilers, Standard Template Library, Cydra 5 dblp
André DeHon	Professor Caltech U, CS cs.caltech.edu/~andre	JPEG 146x196 146x196	reconfigurable hardware, DPGA, MATRIX dblp
José G. Delgado-Frias	Professor Washington State U eecs.wsu.edu/~jdelgado	JPEG 144x181 144x181	VLSI microarchitectures, routers, immunity-/genetic-/neural network-based computing dblp
Robert DeLine	Microsoft Research research.microsoft.com/users/rdeline	?	user interfaces, software engineering, type theory, Vault dblp
James Demmel	Professor UC Berkeley, CS cs.berkeley.edu/~demmel	GIF 113x169 113x169	LAPACK, ScaLAPACK, linear systems, numerical methods dblp
Jack B. Dennis	Professor (emeritus) MIT lcs.mit.edu/people/bioprint.php3?Record_ID=26 Eckert-Mauchly (1984) award	GIF 188x267 188x267	dataflow computers, stream processors dblp
Alvin M. Despain	Professor U of Southern California isi.edu/acal/people/despain.html	GIF 144x174 144x174	computer architecture, multiprocessor systems, logic programming, quantum computation, design automation dblp
Dave Detlefs	Sun Labs East research.sun.com/people/detlefs	GIF 116x142 116x142	Extended Static Checker, Simplify theorem prover, garbage collection dblp
Srinivas Devadas	Professor MIT glenfiddich.lcs.mit.edu/~devadas	JPEG 216x269 216x269	VLSI design, CAD, computer architecture, hardware validation, architectural synthesis for programmable processors, smart caches, security problems in pervasive computing dblp
Keith Diefendorff	Apple	JPEG 127x159 127x159	Apple/PowerPC, AMD K6, Motorola 88110 dblp
Oliver Frank Diessel	Lecturer U of New South Wales, Sydney, Australia cse.unsw.edu.au/~odiessel	GIF 61x72 61x72	design and management of reconfigurable computer systems and applications dblp
Henry G. (Hank) Dietz	Professor U of Kentucky aggregate.org/hankd	JPEG 98x127 98x127	parallel processing, compilers, hardware architectures and networking, operating systems, digital imaging dblp
Edsger Wybe Dijkstra	(deceased) U of Texas, Austin, CS cs.utexas.edu/users/UTCS/report/1997/dijkstra.html Turing (1972) award	JPEG 111x135 111x135	formal methods dblp
David L. Dill	Professor Stanford U verify.stanford.edu/dill	JPEG 75x81 75x81	hardware verification dblp
Chen Ding	Professor U of Rochester, CS cs.rochester.edu/u/cding	JPEG 325x407 325x407	compiler enhancement of global cache reuse, dynamic program analysis and transformation, Smooth, performance tuning and prediction for memory hierarchy dblp
Pedro Diniz	Professor U of Southern California Information Sciences Institute isi.edu/~pedro	JPEG 819x1005 819x1005	commutativity analysis, parallelizing compilers, program analysis, parallel and distributed computing, configurable computing dblp
Stephen W. Director	Dean, College of Engineering U of Michigan engin.umich.edu/director	JPEG 60x83 60x83	design process, statistical VLSI design dblp
David R. Ditzel	CTO Transmeta Corp.	JPEG 65x84 65x84	SPARC, Transmeta dblp
Amer Diwan	Professor U of Colorado, Boulder, CS cs.colorado.edu/~diwan	GIF 114x146 114x146	compiler analyses and optimizations, memory management, memory system performance, power-aware computing, software engineering/visualization tools dblp
Alex Doboli	Professor State U of New York at Stony Brook ece.sunysb.edu/~adoboli	JPEG 113x142 113x142	CAD for embedded systems and Systems-on-Chip, specification/modeling/synthesis of heterogeneous-domain systems dblp
Apostolos Dollas	Professor Technical U of Crete mhl.tuc.gr/PERSONEL/cvs/Dollas_alt2.html	?	rapid system prototyping, computer architecture, reconfigurable computing, embedded systems, application specific high-performance digital systems dblp
Lorenzo Donatiello	Professor U of Bologna, Italy cs.unibo.it/~donat	JPEG 78x98 78x98	performance models of computer and communication systems, performability models of fault-tolerant systems, wireless networks, parallel and distributed simulation dblp
Jack Dongarra	Professor U of Tennessee netlib.org/utk/people/JackDongarra	JPEG 115x154 115x154	numerical algorithms in linear algebra, parallel computing, use of advanced-computer architectures, programming methodology and tools for parallel computers, LINPACK, MPI, PVM, ScaLAPACK dblp
José Duato	Professor Technical U of Valencia, Spain gap.upv.es/people/jduato/english.html	GIF 157x203 157x203	multicomputer systems, interconnection networks, parallel algorithms, simulation dblp
Pradeep Dubey	Intel Research intel.com/research/people/bios/dubey_p.htm	JPEG 95x108 95x108	Altivec, 80386/80486/Pentium, computer architecture, multithreading, multimedia processing dblp
Michel Dubois	Professor U of Southern California, EE usc.edu/dept/ceng/dubois/dubois.html	JPEG 89x105 89x105	multiprocessor architecture/performance/algorithms, rapid prototyping engine for multiprocessors (RPM) dblp
Evelyn Duesterwald	IBM	?	interprocedural data flow analyses dblp
Carole Dulong	co-manager, IA-64 compiler group Intel	GIF 61x77 61x77	MMX, IA-64 compilation dblp
Nikil Dutt	Professor UC Irvine cecs.uci.edu/~dutt	JPEG 173x226 173x226	embedded systems design automation dblp
Shantanu Dutt	Professor U of Illinois at Chicago, ECE ece.uic.edu/~dutt	JPEG 203x275 203x275	parallel and distributed computing, place and route, fault-tolerant circuits, multicomputer architecture dblp
Robert W. Dutton	Professor Stanford U, EE www-tcad.stanford.edu/tcad/bios/dutton.html	JPEG 137x189 137x189	MEMS, CAD Tools, Parascope, Pisces, Suprem dblp
Vaclav Dvorak	Professor Brno U of Technology, Czech Republic fee.vutbr.cz/~dvorak	JPEG 80x101 80x101	computer architecture, parallel and distributed computing, embedded and configurable systems dblp
Sandhya Dwarkadas	Professor U of Rochester, CS cs.rochester.edu/u/sandhya	GIF 178x195 178x195	InterWeave, CASHMERE, ARCH: Architecture, Runtime, and Compiler integration for HPC, processing for low-power, InterAct dblp
Harry Dwyer	Bell Labs, Lucent cm.bell-labs.com/who/dwyer	GIF 96x124 96x124	out-of-order processors dblp
Matthew B. Dwyer	Professor Kansas State U cis.ksu.edu/~dwyer	JPEG 533x713 533x713	software verification, Bandera, model checking, specification dblp
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Kemal Ebcioglu	IBM T. J. Watson	?	VLIW, dynamic compilation dblp
Carl Ebeling	Professor U of Washington, Seattle, CS cs.washington.edu/homes/ebeling	JPEG 368x505 368x505	RaPiD, reconfigurable hardware dblp
Hans Eberle	senior staff engineer Sun Research research.sun.com/people/eberle	JPEG 83x110 83x110	interconnetion networks, clusters dblp
Stephen A. Edwards	Professor Columbia U, CS cs.columbia.edu/~sedwards	JPEG 154x192 154x192	embedded system design, domain-specific languages, compilers dblp
Lieven Eeckhout	postdoc Ghent U, Belgium elis.rug.ac.be/~leeckhou/	JPEG 101x165 101x165	computer architecture, performance analysis, statistical modeling, analytical modeling, early design stage modeling dblp
Gregory K. Egan	Professor Monash U, Australia ecse.monash.edu.au/staff/egan	GIF 106x136 106x136	design / programming / applications of high-performance parallel computer architectures dblp
Susan J. Eggers	Professor U of Washington Seattle, CS cs.washington.edu/homes/eggers	JPEG 305x311 305x311	DyC dynamic compilation, SMT simultaneous multithreading, SPIN dblp
Thorsten von Eicken	Professor (visiting) UC Santa Barbara, CS cs.ucsb.edu/~tve	GIF 129x167 129x167	Active Messages, Split-C, U-Net dblp
Rudolf Eigenmann	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~eigenman	GIF 97x127 97x127	parallel computing, optimizing compilers, software engineering, characterization of applications, performance evaluation and benchmarking dblp
Christine Eisenbeis	INRIA, Rocquencourt, France www-rocq.inria.fr/~eisenbei	JPEG 217x195 217x195	register allocation, software pipelining dblp
Magnus Ekman	Sun microsystems ce.chalmers.se/~mekman	JPEG 73x100 73x100	energy-efficient architecture, statistical techniques for architectural simulation, large memories dblp
Ahmed A. El-Amawy	Professor Louisiana State U ece.lsu.edu/amawy/amawy.html	JPEG 151x202 151x202	parallel processing, computer architecture, clock distribution, fault tolerant computing, interconnection networks dblp
Tarek El-Ghazawi	Professor George Washington U seas.gwu.edu/~tarek	JPEG 344x435 344x435	high-performance computing, parallel computer architectures, high-performance I/O, reconfigurable computing, experimental performance evaluations, computer vision, remote sensing dblp
Petru Eles	Professor Linkoping U, Linkoping, Sweden ida.liu.se/~petel	JPEG 125x166 125x166	electronic design automation, hardware/software co-design, real-time systems, design of embedded systems, design for testability dblp
Joel Emer	Director Intel Microarchitecture Research intel.com/pressroom/kits/bios/jemer.htm	JPEG 252x349 252x349	microarchitecture, Alpha microprocessors, quantitative analysis, performance modeling, SMT, prediction dblp
E. Allen Emerson	Professor U of Texas, Austin, CS cs.utexas.edu/users/emerson	GIF 128x139 128x139	model checking dblp
Dawson R. Engler	Professor Stanford U stanford.edu/~engler	JPEG 104x138 104x138	Exokernel, tickC, metacompilation dblp
Michael D. Ernst	Professor MIT sdg.lcs.mit.edu/~mernst	GIF 87x105 87x105	program analysis, compilers dblp
Rolf Ernst	Professor Technical U of Braunschweig ida.ing.tu-bs.de/people/ernst/home.e.shtml	JPEG 109x142 109x142	computer architecture, digital circuits, computer engineering dblp
M. Anton Ertl	Professor Technische U Wien, Austria complang.tuwien.ac.at/anton/home.html	?	compiler back-ends, Forth, interpreters, constraint logic programming, Linux and operating systems dblp
Roger Espasa	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/roger	JPEG 58x75 58x75	vector architectures dblp
Daniel Etiemble	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~de	JPEG 98x130 98x130	performance evaluation of clusters of multiprocessors and PCs, multivalued logic circuits dblp
William S. Evans	Professor U of British Columbia, Canada cs.ubc.ca/~will	JPEG 89x128 89x128	information theory, data compression, computational geometry dblp
Guy Even	Professor Tel Aviv U, Israel eng.tau.ac.il/~guy	?	approximation algorithms for NP Complete problems related to VLSI, computer arithmetic, design of floating point units, systolic arrays dblp
Marius Evers	AMD	?	branch prediction dblp
Paraskevas Evripidou	Professor U of Cyprus cs.ucy.ac.cy/~skevos	JPEG 82x97 82x97	parallel programming and debugging, pararallelizing compilers dblp
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Manuel A. Fähndrich	Microsoft Research research.microsoft.com/~maf	?	static program analysis, type systems, novel programming languages, Fugue, Vault, BANE dblp
Michael Faiman	(deceased) U of Illinois at Urbana-Champaign, CS cs.uiuc.edu/people/faculty/faiman.html	JPEG 100x121 100x121	computer architecture, computer networks, ILLIAC I & II, graphical processing, device theory, circuit design dblp
Babak Falsafi	Professor Carnegie Mellon U, ECE ece.cmu.edu/~babak	JPEG 120x158 120x158	microarchitecture, multiprocessors, memory coherence dblp
Jesse Z. Fang	Director Intel MRL Programming Systems Lab intel.com/research/people/bios/fang_j.htm	?	compiler/architecture research for ILP and threads, dynamic optimization for C/C++, object oriented languages, virtual machines and just-in-time compilation dblp
Paolo Faraboschi	Hewlett-Packard Labs, Cambridge	JPEG 105x147 105x147	embedded computers, custom-fit processors dblp
Keith I. Farkas	Hewlett Packard WRL research.compaq.com/wrl/people/farkas/bio.html	JPEG 101x129 101x129	low power, processor architecture, memory system performance dblp
Matthew K. Farrens	Professor UC Davis, CS huron.cs.ucdavis.edu/~farrens	GIF 70x91 70x91	architecture and design of high-performance single-chip processors dblp
Stuart Feldman	Director IBM Institute for Advanced Commerce research.ibm.com/iac/advisory-feldman.html	GIF 117x136 117x136	software engineering, programming languages, scientific computing, make dblp
Edward W. Felten	Professor Princeton U, CS cs.princeton.edu/~felten	JPEG 152x189 152x189	secure internet programming, SHRIMP multicomputer dblp
Jeanne Ferrante	Professor UC San Diego www-cse.ucsd.edu/users/ferrante	JPEG 144x176 144x176	SSA, predicated execution, compiler optimizations dblp
John Field	Research staff IBM Research research.ibm.com/people/j/jfield	JPEG 84x105 84x105	program understanding and analysis tools, algorithms for program analysis, logics of programs, term- and graph-rewriting, program slicing, compiler optimization, incremental algorithms dblp
Tony Field	Senior Lecturer and Teaching Fellow Imperial College, UK doc.ic.ac.uk/~ajf	?	performance modelling of computer software and hardware, software performance optimisation, particle-based simulation of microbiological systems, discrete-event simulation, functional programming languages, compilers and run-time systems dblp
Robert Bruce Findler	Professor U of Chicago cs.uchicago.edu/people/robby	JPEG 118x160 118x160	programming languages, DrScheme, software contracts dblp
Ulrich Finger	Director Institut Eurecom, France eurecom.fr/Resources/Direction/finger.html	GIF 85x101 85x101	parallel processing, parallel computer architecture dblp
Alan M. Finn	United Technologies Research Center users.erols.com/alanfinn	GIF 346x417 346x417	computer architecture with emphasis on embedded systems dblp
Charles N. Fischer	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~fischer/fischer.html	GIF 162x231 162x231	compilers, register allocation dblp
Joseph A. Fisher	Hewlett-Packard Labs, Cambridge hpl.hp.com/about/bios/josh_fisher.html Eckert-Mauchly (2003) award	JPEG 81x95 81x95	ILP, branch prediction, VLIW, trace scheduling dblp
Kathleen Fisher	AT&T Research research.att.com/info/kfisher	JPEG 95x132 95x132	domain-specific programming languages, Moby, PADS, Hancock dblp
Cormac Flanagan	Professor UC Santa Cruz CS soe.ucsc.edu/~cormac	GIF 125x171 125x171	software engineering, validation, defect detection dblp
Matthew Flatt	Professor U of Utah CS cs.utah.edu/~mflatt	JPEG 66x83 66x83	programming languages, DrScheme, object-oriented programming, high-level operating systems dblp
Michael J. Flynn	Professor (emeritus) Stanford U umunhum.stanford.edu/~flynn Eckert-Mauchly (1992) award	JPEG 236x342 236x342	computer architecture dblp
José A. B. Fortes	Professor U of Florida acis.ufl.edu/fortes	JPEG 195x250 195x250	parallel processing, computer architecture, network-computing, fault-tolerant computing dblp
Jeff P. Foster	Professor U of Maryland, CS cs.umd.edu/~jfoster	JPEG 143x190 143x190	tools and techniques to improve software quality, cqual dblp
Matthew Frank	Professor U of Illinois at Urbana-Champaign, ECE ece.uiuc.edu/faculty/faculty.asp?mif	JPEG 378x446 378x446	parallelization of programs with statically unpredictable dependencies, RAW dblp
Michael P. Frank	Professor U of Florida ECE cise.ufl.edu/~mpf	JPEG 186x240 186x240	low-power computing, reversible computing, adiabatic circuits, reversible languages dblp
Manoj Franklin	Professor U of Maryland ece.umd.edu/~manoj	JPEG 154x190 154x190	computer architecture especially ILP, compiling for ILP machines, memory systems dblp
Mark A. Franklin	Professor Washington U in St. Louis ccrc.wustl.edu/~jbf	GIF 194x258 194x258	computer architecture, parallel processing, systems performance evaluation, VLSI design dblp
Michael Franz	Professor UC Irvine ics.uci.edu/~franz	JPEG 156x217 156x217	security and efficiency of mobile code, code compression, dynamic compilation, compiling for low-power dblp
Paul Franzon	Professor North Carolina State U, ECE ece.ncsu.edu/erl/faculty/paulf.html	GIF 182x237 182x237	high speed packaging and interconnect, high speed and low power chip design, micro electro mechanical machines, wafer-scale integration, IC yield modeling, VLSI chip design, communications systems design, molecular computers dblp
Christopher W. Fraser	Microsoft Research research.microsoft.com/~cwfraser/	JPEG 79x82 79x82	code compression, code generation, editors dblp
Eby G. Friedman	Professor U of Rochester, EE ee.rochester.edu/users/friedman	GIF 144x200 144x200	VLSI circuits and systems, CMOS circuits, synchronization, clock distribution, pipelining, speed/power/area tradeoffs dblp
Jason Fritts	Professor Washington U in St. Louis ccrc.wustl.edu/~jefritts	JPEG 109x147 109x147	media processors, embedded systems, ubiquitous computing, computer architecture, parallel processing, video and image processing dblp
W. Kent Fuchs	Professor Cornell U, ECE composer.ecn.purdue.edu/~fuchs (old)	JPEG 106x137 106x137	dependable computer systems, testing and fault diagnosis of VLSI IC dblp
Donald S. Fussell	Professor U of Texas, Austin, CS cs.utexas.edu/users/fussell	GIF 130x161 130x161	computer architecture, computer graphics, database systems, design automation, fault-tolerant computing dblp
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Richard P. Gabriel	Sun Labs dreamsongs.com/Bio.html Allen Newell ((2004)) award	JPEG 138x162 138x162	Lisp, CLOS dblp
Daniel D. Gajski	Professor UC Irvine cecs.uci.edu/~gajski	JPEG 155x200 155x200	requirement/specification/design of embedded systems dblp
Abbas El Gamal	Professor Stanford U, ECE www-isl.stanford.edu/~abbas	JPEG 114x150 114x150	information theory, communication complexity, VLSI design and CAD, programmable digital cameras dblp
Gregory R. Ganger	Professor Carnegie Mellon U, ECE ece.cmu.edu/~ganger	JPEG 98x132 98x132	BSD FFS, exokernel, MEMS storage, DiskSim dblp
Jack Gannsle	editor Embedded Systems Programming ganssle.com	GIF 65x79 65x79	embedded systems
Guang R. Gao	Professor U of Delaware capsl.udel.edu/~ggao	JPEG 61x69 61x69	computer architecture and systems, parallel and distributed systems, computational biology and bioinformatics, optimizing and parallelizing compilers, parallel programming, VLSI and application-specific system design dblp
Jean-Luc Gaudiot	Professor UC Irvine, EECS ece.uci.edu/faculty/gaudiot	GIF 118x158 118x158	parallel processing, functional languages, processor architecture, fault-tolerand computing dblp
Alan D. George	Professor U of Florida hcs.ufl.edu/~george	JPEG 151x190 151x190	high-performance computer networks, parallel and distributed computing, high-performance computer architecture, fault-tolerant computing dblp
Manuel G. Gericota	Professor Polytechnic Instutute of Porto, ECE, Portugal dee.isep.ipp.pt/~mgg/indexe.html	JPEG 89x111 89x111	design and test of digital systems, FPGA design and test, test methodologies for reconfigurable hardware systems, dynamic allocation of hardware resources in dynamically reconfigurable systems, reconfigurable systems management dblp
Rob Gerth	staff engineer Strategic CAD Labs, Intel	GIF 53x69 53x69	multi-processor verification dblp
Kourosh Gharachorloo	Google geocities.com/kourosh_info Maurice Wilkes (2004) award	JPEG 105x133 105x133	high-end servers, Shasta, DASH, parallel computer architecture and software, commercial database and webserver performance dblp
Giorgio Ghelli	Professor U of Pisa, Italy di.unipi.it/~ghelli/ghelli.html	JPEG 220x240 220x240	spatial logics, database programming languages, type theory dblp
Kanad Ghose	Professor Binghamton State U of New York, CS cs.binghamton.edu/~ghose	JPEG 215x291 215x291	computer architecture, parallel and distributed processing, high-performance networking, VLSI systems, large-scale volume visualization dblp
Garth A. Gibson	Professor Carnegie Mellon U, CS cs.cmu.edu/~garth	JPEG 169x204 169x204	RAID, storage, NASD dblp
Yossi Gil	Professor Israel Institute of Technology (Technion) cs.technion.ac.il/~yogi	JPEG 70x100 70x100	software engineering, object-oriented pardigm, programming languages, parsing dblp
Roberto Giorgi	Professor U di Siena, Italy lucy.dii.unisi.it/~giorgi	JPEG 81x92 81x92	coherence protocols for multiprocessors, behavior of user and system code, architectural simulation, multithreaded processors dblp
Tony Givargis	Professor UC Irvine cecs.uci.edu/~givargis	JPEG 210x277 210x277	embedded system design and optimization dblp
Andy Glew	Intel Microprocessor Research Labs intel.com/research/mrl/people/glew_a.htm	GIF 100x115 100x115	microarchitecture, P6, MMX dblp
Neal Glew	Intel Research intel.com/research/people/bios/glew_n.htm	JPEG 60x84 60x84	typed assembly language dblp
Maya Gokhale	Sarnoff Corp	JPEG 188x186 188x186	reconfigurable hardware, C to HDL dblp
Seth Copen Goldstein	Professor Carnegie Mellon U, CS cs.cmu.edu/~seth	JPEG 108x109 108x109	reconfigurable hardware, PipeRench, nanotechnology, lazy threads dblp
German S. Goldszmidt	IBM T. J. Watson cs.columbia.edu/~german (old)	GIF 195x240 195x240	distributed debugging, programming languages for distributed systems, e-commerce, distributed systems dblp
Ronaldo A. L. Gonçalves	Professor U Estadual de Maringa, Brazil din.uem.br/~ronaldo	JPEG 313x395 313x395	parallel and high performance computing, parallel / superscalar / multithreaded architectures, performance evaluation of computer architecture, operating systems and compilers dblp
Georges Gonthier	Microsoft Research Cambridge research.microsoft.com/~gonthier	GIF 94x125 94x125	four-color theorem, programming languages, program verification, lambda calculus dblp
Antonio Gonzalez	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/antonio	JPEG 153x186 153x186	superscalar processors dblp
José González	Professor U de Murcia, Spain ditec.um.es/~joseg	GIF 101x123 101x123	value prediction, CC-NUMA, microarchitecture dblp
James R. Goodman	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~goodman	JPEG 108x132 108x132	high-performance computer architecture, memory systems, shared-memory multiprocessing dblp
David W. Goodwin	principal engineer Hewlett-Packard VSSAD group (old)	GIF 65x84 65x84	binary optimizations, Alpha performance analysis, Spike, executable interprocedural dataflow analysis dblp
Gerhard Goos	Professor U Karlsruhe, Germany i44w3.info.uni-karlsruhe.de/~ggoos	JPEG 110x149 110x149	object-oriented programming, software components, compiler correctness, VERIFIX dblp
Ganesh Gopalakrishnan	Professor U of Utah, CS cs.utah.edu/~ganesh	GIF 177x237 177x237	Utah Verifier (UV), formal verification, asynchronous circuits and systems dblp
Michael J. C. Gordon	Professor Cambridge U, UK cl.cam.ac.uk/users/mjcg	JPEG 109x128 109x128	HOL, formal verification dblp
James Gosling	Sun Labs java.sun.com/people/jag	JPEG 126x154 126x154	Java, Emacs, NeWS window system dblp
Allan Gottlieb	Professor New York U, CS cs.nyu.edu/cs/faculty/gottlieb	GIF 155x212 155x212	Ultracomputer, parallel computers dblp
Ramaswamy Govindarajan	Professor Indian Institute of Science, Bangalore, India serc.iisc.ernet.in/~govind	GIF 80x104 80x104	ILP compilation, compilation techniques for architectural features, compilation for embedded/DSP processors, distributed shared memory, high performance architectures, programming models for DSP dblp
Susan L. Graham	Professor UC Berkeley, CS cs.berkeley.edu/~graham	GIF 102x138 102x138	parsing, compiler construction, gprof dblp
F. Gail Gray	Professor Virginia Tech, EE ecpe.vt.edu/faculty/gray.html	JPEG 73x93 73x93	VHDL, high level modeling and design, high level test generation, fault tolerant systems, reconfigurable arrays, coding theory dblp
Jim Gray	Microsoft Research research.microsoft.com/~gray Turing (1998) award	GIF 158x218 158x218	transactions, databases, scalable servers dblp
Ronald I. Greenberg	Professor Loyola U, Chicago math.luc.edu/~rig	JPEG 249x338 249x338	algorithms, parallel computation, computer architecture, VLSI, discrete mathematics dblp
Mark R. Greenstreet	Professor U of British Columbia CS, CA cs.ubc.ca/~mrg	JPEG 70x88 70x88	VLSI design and verification, hybrid systems, dynamical systems, formal methods, asynchronous logic dblp
David Gregg	Professor Trinity College, Dublin, Ireland cs.tcd.ie/David.Gregg	JPEG 206x211 206x211	interpreters, hardware compilation, compiling for instruction level parallelism, software pipelining, register allocation, branch prediction dblp
Ed Grochowski	Intel MRL intel.com/research/people/bios/grochowski_e.htm	JPEG 90x108 90x108	Intel 486/Pentium/Pentium II/Itanium dblp
Thomas R. Gross	Professor ETH Zurich, Switzerland lst.inf.ethz.ch/people/trg.html	GIF 192x256 192x256	MIPS, Warp, iWarp, Fx dblp
Dan Grossman	Professor U of Washington, Seattle, CS cs.washington.edu/homes/djg	JPEG 304x382 304x382	Cyclone, type theory dblp
Andrew Grove	Chairman of the Board Intel developer.intel.com/pressroom/kits/bios/grove.htm	JPEG 196x256 196x256	semiconductors, Intel
Orna Grumberg	Professor Israel Institute of Technology (Technion) cs.technion.ac.il/users/orna	JPEG 82x97 82x97	computer-aided verification of software and hardware, modularity, abstraction, refinement and counterexamples, symmetry, temporal logics, equivalences and preorders, distributed model checking, static analysis and model checking, coverage and vacuity, sat-based model checking, games for model checking, automata on infinite objects dblp
Dirk Grunwald	Professor U of Colorado, CS cs.colorado.edu/~grunwald	JPEG 92x128 92x128	computer systems dblp
Michael K. Gschwind	Researcher IBM TJ Watson Research Center research.ibm.com/people/m/mikeg	JPEG 105x131 105x131	dynamic compilation, binary translation, dynamic optimization, BOA, DAISY, system architecture, microarchitecture (RS6000 and S/390), compilation, power-modelling and power-aware architecture, application-specific processors, SOC dblp
P. Glenn Gulak	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~gulak	GIF 186x263 186x263	VLSI in digital communications and signal processing, computer architecture, VLSI design and applications dblp
Carl A. Gunter	Professor U of Illinois at Urbana-Champaign CS www-faculty.cs.uiuc.edu/~cgunter/	JPEG 135x160 135x160	security, networks, programming languages, software engineering dblp
Anoop Gupta	Senior Researcher Microsoft Research research.microsoft.com/~anoop	JPEG 112x142 112x142	DASH, FLASH, multimedia dblp
Rajesh Gupta	Professor UC Irvine ics.uci.edu/~rgupta	GIF 133x174 133x174	algorithms for VLSI design automation, CAD for embedded and portable systems, computer architecture dblp
Rajiv Gupta	Professor U of Arizona, CS cs.arizona.edu/people/gupta	JPEG 147x197 147x197	path-sensitive optimizations, compiler back-end dblp
Sumit Gupta	Tallwood Venture Capital cecs.uci.edu/~sumitg	JPEG 250x299 250x299	SPARK, high-level synthesis, reconfigurable computing dblp
John R. Gurd	Professor U of Manchester, UK cs.man.ac.uk/cnc/staff/john/home.html	GIF 71x89 71x89	Manchester data-flow computer, parallel computer systems dblp
Samuel Z. Guyer	postdoc U of Texas Austin CS cs.utexas.edu/users/sammy	JPEG 101x135 101x135	high-level optimizations, domain-specific optimizations, pointer analysis, automatic error checking, compiler-assisted memory management dblp
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Haldun Hadimioglu	Professor Polytechnic U, NY cis.poly.edu/haldun	JPEG 124x161 124x161	high-speed optical switch design, novel processor design, memory hierarchy issues and I/O dblp
Erik Hagersten	Professor Uppsala U, Sweden docs.uu.se/~eh	GIF 151x218 151x218	shared-memory multiprocessor architectures, cache-only memory architectures (COMA), dynamic caching algorithms, access pattern categorization, dynamically adapting architectures dblp
Ibrahim N. Hajj	Professor U of Illinois at Urbana-Champaign, ECE ece.uiuc.edu/faculty/faculty.asp?i-hajj	JPEG 117x142 117x142	CAD, VLSI circuits and systems dblp
Mary W. Hall	Professor U of Southern California isi.edu/~mhall	?	DIVA: Data-IntensiVe Architecture, DEFACTO: Design Environment for Adaptive Computing TechnOlogy, combining compile-time and run-time parallelization dblp
Richard W. Hamming	(deceased) Bell Labs, Lucent/Naval Postgraduate School cm.bell-labs.com/cm/cs/alumni/hamming Turing (1968) award	JPEG 175x254 175x254	error correcting codes, programming languages, numerical analysis, digital filters dblp
Richard E. Hank	Hewlett-Packard crhc.uiuc.edu/IMPACT/people/graduated/Rick_Hank.html (old)	JPEG 121x155 121x155	region-based compilation, VLIW and EPIC compilation dblp
Chris Hankin	Professor Imperial College, UK doc.ic.ac.uk/chris.html	JPEG 154x219 154x219	program analysis, safety critical systems, coordination languages dblp
Robert Harper	Professor Carnegie Mellon U, CS www-2.cs.cmu.edu/~rwh	JPEG 48x64 48x64	programming languages design/semantics/verification/implementation, types in compilation, logical frameworks and meta-languages, scientific computing, trustless grid computing dblp
Tim Harris	Researcher Microsoft Research Cambridge, UK research.microsoft.com/~tharris	JPEG 75x75 75x75	programming languages, managed runtime environments, multi-threaded software, transactional programming dblp
Reiner Hartenstein	Professor U Kaiserslautern, Germany hartenstein.de	JPEG 184x223 184x223	reconfigurable computing/supercomputing/computer architectures/SoC, FPGAs, software/configware co-compilation, hardware description languages, microprogramming dblp
Soha Hassoun	Professor Tufts U eecs.tufts.edu/~soha	GIF 122x131 122x131	architectural and sequential optimizations, timing analysis, regularity extraction, configurable computing dblp
Scott Hauck	Professor U of Washington Seattle, EE ee.washington.edu/faculty/hauck	JPEG 71x94 71x94	reconfigurable hardware, Chimaera dblp
John P. Hayes	Professor U of Michigan eecs.umich.edu/~jhayes	GIF 124x180 124x180	quantum computers, massively parallel embedded systems, computer architectures for safety-critical applications, verification and testing of systems-on-a-chip, automated synthesis and layout dblp
Lei He	Professor U of Wisconsin-Madison engr.wisc.edu/ece/faculty/he_lei.html	GIF 150x200 150x200	CAD for VLSI, power-efficient circuits and computer systems, numerical and combinatorial optimization dblp
Xubin He	Professor Tennessee Tech U, ECE ece.tntech.edu/hexb	JPEG 96x108 96x108	storage cache and disk I/O, networked storage, VHDL, performance evaluation dblp
Görel Hedin	Professor Lund Institute of Technology, Sweden cs.lth.se/home/Gorel_Hedin/	JPEG 101x126 101x126	object-oriented languages and design, domain-specific languages, language implementation techniques, interactive software development environments dblp
Jan Heering	Professor Centrum voor Wiskunde en Informatica, Netherlands homepages.cwi.nl/~jan	?	compilers, program restructuring, software engineering dblp
Eric C. R. Hehner	Professor U of Toronto, CS, Canada cs.toronto.edu/~hehner	JPEG 153x179 153x179	formal methods of program design, programming language semantics, compiler design, high-level circuit design dblp
John Heinlein	Transmeta www-flash.stanford.edu/~heinlein	JPEG 141x199 141x199	FLASH dblp
Mark Heinrich	Professor University of Central Florida, CS csl.cs.ucf.edu/~heinrich	JPEG 593x902 593x902	active memory and I/O subsystems, novel computer architectures, parallel computer architecture, data-intensive computing, scalable cache coherence protocols, multiprocessor design and simulation methodology, hardware/software co-design dblp
Nevin Heintze	Agere Systems cm.bell-labs.com/cm/cs/who/nch	JPEG 93x116 93x116	set-based analysis, pointer analysis, verification dblp
Laurie J. Hendren	Professor McGill U, Montreal, Canada sable.mcgill.ca/~hendren	GIF 74x98 74x98	compilers, pointer analyses, McCAT, Soot dblp
John L. Hennessy	Professor Stanford U www-flash.stanford.edu/~jlh von Neumann Medal (2000), Eckert-Mauchly (2001) award	GIF 100x115 100x115	FLASH, MIPS dblp
Dana S. Henry	Professor Yale U, CS thor.cs.yale.edu/~dana	GIF 85x113 85x113	Ultrascalar, NIC, FLIP dblp
Thomas A. Henzinger	Professor U of California at Berkeley, ECE www-cad.eecs.berkeley.edu/~tah	GIF 150x188 150x188	system design/modeling/implementation/verification, formal verification, embedded systems dblp
Martin C. Herbordt	Professor Boston U ? people.bu.edu/herbordt	JPEG 170x202 170x202	architecture and evaluation of massively parallel computers, network caching dblp
Maurice Herlihy	Professor Brown U CS cs.brown.edu/people/mph/home.html	JPEG 48x60 48x60	distributed computing, transactional memory, lock-free programming dblp
Paul N. Hilfinger	Professor UC Berkeley, CS cs.berkeley.edu/~hilfingr	GIF 114x168 114x168	Lisp, Titanium (Java), PRCS dblp
Mark D. Hill	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~markhill	JPEG 256x299 256x299	multiprocessors, system architecture, DSM, cache memory dblp
Sébastien Hily	senior researcher Intel Microprocessor Research Labs irisa.fr/caps/people/hily/index_en.htm (old)	GIF 109x141 109x141	microprocessors, computer architecture, simultaneous multithreading dblp
Michael Hind	Researcher IBM T. J. Watson research.ibm.com/people/h/hind/	JPEG 348x475 348x475	Jikes, interprocedural analysis, automatic parallelization, dynamic optimization dblp
Glenn J. Hinton	director of IA-32 Microarchitecture Development Intel intel.com/pressroom/kits/bios/hinton.htm Maurice Wilkes (2002) award	JPEG 63x82 63x82	i960, Pentium Pro, Pentium II, Pentium 4
Ralf Hinze	Professor U Bonn, Germany /www.informatik.uni-bonn.de/~ralf	JPEG 456x586 456x586	functional programming, Haskel dblp
C. Antony R. Hoare	Microsoft Research, Cambridge, UK research.microsoft.com/~thoare Turing (1980) award	GIF 180x233 180x233	programming methods and languages, proof techniques for programs, distributed computing, hardware compilation,P dblp
James C. Hoe	Professor Carnegie Mellon U, ECE ece.cmu.edu/~jhoe	GIF 93x108 93x108	operation-centric hardware synthesis, term-rewriting systems, network interfaces for clusters dblp
Martin Hofmann	Professor Ludwig-Maximilians U Muenchen tcs.informatik.uni-muenchen.de/~mhofmann	GIF 150x214 150x214	type theory, principles of programming languages, semantics, category theory, mathematical logic, formal methods dblp
H. Peter Hofstee	IBM Austin Research Lab	?	parallel algorithms, microarchitecture, timing analysis, asynchronous circuits, logic design dblp
Urs Hölzle	Professor UC Santa Barbara, CS cs.ucsb.edu/~urs	JPEG 200x278 200x278	object-oriented programming languages, software engineering, OSUIF, StrongTalk, HotSpot JVM, indirect branch prediction dblp
Gerard J. Holzmann	Bell Labs cm.bell-labs.com/cm/cs/who/gerard	GIF 81x93 81x93	SPIN, model checking dblp
Sangjin Hong	Professor State U of New York at Stony Brook ECE ece.sunysb.edu/~snjhong/	JPEG 82x97 82x97	low power VLSI, digital signal processing, embedded designs dblp
Mark Horowitz	Professor Stanford U www-flash.stanford.edu/~horowitz	GIF 75x100 75x100	FLASH, CAD tools, low power design dblp
R. Nigel Horspool	Professor U of Victoria, Canada cs.uvic.ca/~nigelh	JPEG 331x415 331x415	compilers, programming language (Java) implementations, document conversion, data compression, XML, HTML, string search dblp
Susan B. Horwitz	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~horwitz/horwitz.html	JPEG 133x133 133x133	language-based programming environments, program slicing differencing and merging, static analysis, interprocedural dataflow analysis dblp
Antony L. Hosking	Professor Purdue U, CS cs.purdue.edu/homes/hosking	JPEG 363x499 363x499	programming language design and implementation, database and persistent programming languages, object-oriented database systems, dynamic memory management, compiler optimization, architectural support for programming languages and applications dblp
Michael S. Hsiao	Professor Virginia Tech, ECE visc.vt.edu/~mhsiao	JPEG 138x165 138x165	test and verification, CAD, low-power architecture dblp
Wilson C. Hsieh	Professor U of Utah, CS cs.utah.edu/~wilson	?	compilers, programming languages, systems, architecture dblp
Wei-Chung Hsu	Professor U of Minesotta, CS www-users.cs.umn.edu/~hsu	JPEG 196x237 196x237	high performance processor and system architectures, compiler optimizations, runtime optimization systems dblp
Y. Charlie Hu	Professor Purdue U, ECE ece.purdue.edu/~ychu	JPEG 61x73 61x73	distributed systems, operating systems, networking, high performance computing dblp
Yiming Hu	Professor U of Cincinnati ececs.uc.edu/~yhu	GIF 113x135 113x135	memory architecture, high performance I/O systems, file systems, virtual memory, high performance Web servers, embedded systems, parallel and distributed computing dblp
Michael C. Huang	Professor U of Rochester, ECE ece.rochester.edu/~mihuang	JPEG 130x162 130x162	computer architecture, processor microarchitecture, energy-efficient system and processor architecture, processing-in-memory dblp
Ali R. Hurson	Professor Penn State U cse.psu.edu/~hurson	GIF 191x267 191x267	conventional and unconventional concurrent and parallel systems, object oriented databases, multi-databases, hybrid dataflow architecture, global information processing in mobile and wireless environments dblp
Brad L. Hutchings	Professor Brigham Young U, EE ee.byu.edu/faculty/hutch	JPEG 128x166 128x166	application-specific processors, run-time reconfiguration, automatic target recognition dblp
Kai Hwang	Professor U of Southern California ceng.usc.edu/~kaihwang	JPEG 100x114 100x114	computer architecture, digital arithmetic, parallel processing, distributed computing dblp
Wen-mei W. Hwu	Professor U of Illinois Urbana-Champaign, ECE crhc.uiuc.edu/Faculty/hwu.html Maurice Wilkes (1998) award	JPEG 161x213 161x213	IMPACT, Trimaran, computer architecture, compilers dblp
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Paolo Ienne	Professor Ecole Polytechnique Federale de Lausanne, Switzerland lapwww.epfl.ch/people/ienne	JPEG 99x135 99x135	computer and processor architecture, language-based VLSI design flows, computer arithmetic, systolic array processors, hardware for neural networks, design for testability dblp
Roberto Ierusalimschy	Professor PUC-Rio, Brazil inf.puc-rio.br/~roberto	JPEG 171x225 171x225	domain-specific languages dblp
Liviu Iftode	Professor U of Maryland, CS cs.umd.edu/~iftode	JPEG 436x561 436x561	operating systems, distributed systems, networking, embedded and pervasive computing, distributed shared memory dblp
Masaharu Imai	Professor Osaka U, Japan vlsilab.ics.es.osaka-u.ac.jp/~imai	JPEG 67x88 67x88	application-specific processors dblp
Mary Jane Irwin	Professor Penn State U cse.psu.edu/~mji	JPEG 169x248 169x248	computer architecture, computer arithmetic, VLSI systems design, low power design, electronic design automation dblp
Randall D. Isaac	Vice President of Systems, Technology, and Science IBM Research	JPEG 55x66 55x66	semiconductor technology dblp
Ravishankar K. Iyer	Professor U of Illinois at Urbana-Champaign, ECE crhc.uiuc.edu/Faculty/iyer.html	GIF 116x144 116x144	scientific/commercial workload characterization, interconnection networks, memory systems, latency hiding techniques, performance evaluation dblp
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Bruce Jacob	Professor U of Maryland, EE ee.umd.edu/~blj	JPEG 101x149 101x149	computer architecture and microarchitecture, memory hierarchies, embedded systems, Verilog modeling, low-level operating systems design, computer music dblp
T. Matthew Jacob	Professor Indian Institute of Science, Bangalore, India csa.iisc.ernet.in/people/faculty/data/mjt.htm	?	performance aspects of computer architecture, operating systems, parallel processing
Quinn Jacobson	Sun	JPEG 169x206 169x206	trace processors dblp
Margarida F. Jacome	Professor U of Texas, Austin, ECE horizon.ece.utexas.edu/~jacome	GIF 115x143 115x143	embedded VLIW/EPIC processors, retargetable compilers, system-level design, hardware/software codesign, high-level synthesis dblp
Joxan Jaffar	Professor National University Singapore comp.nus.edu.sg/~joxan	JPEG 210x289 210x289	programming languages and applications, logic and constraint programming, program analysis and verification dblp
Suresh Jagannathan	Professor Purdue U, CS cs.purdue.edu/homes/suresh	JPEG 260x341 260x341	program analysis and compiler design, peer-to-peer computing, distributed storage architectures dblp
Axel Jantsch	Professor Royal Institute of Technology, Stockholm, Sweden ele.kth.se/~axel	JPEG 480x640 480x640	MASCOT, VLSI design and synthesis, system level specification/modelling/validation dblp
Alan Jeffrey	Professor DePaul U, Chicago, IL fpl.cs.depaul.edu/ajeffrey	JPEG 170x199 170x199	foundations of programming languages and computer security, semantics of higher order languages, mathematical models of object-based systems, type systems, concurrent and distributed languages dblp
Stephen Jenks	Professor UC Irvine, ECE ece.uci.edu/~sjenks	JPEG 114x148 114x148	parallel computing, large-scale distributed memory systems, thread migration, real-time distributed systems dblp
Tor E. Jeremiassen	Texas Instruments cm.bell-labs.com/cm/cs/who/tor (old)	JPEG 786x1107 786x1107	computer architecture, DSPs, compilers dblp
Ahmed Amine Jerraya	TIMA Laboratory, IMAG, Grenoble, France tima-cmp.imag.fr/Homepages/jerraya/jerraya.html	GIF 98x117 98x117	hardware-software co-design dblp
Chris Jesshope	Professor U of Amsterdam CS, Netherlands carol.science.uva.nl/~jesshope/	JPEG 125x144 125x144	microarchitecture, e-learning
Somesh Jha	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~jha	JPEG 133x133 133x133	software engineering, model checking, security dblp
Daniel A. Jiménez	Professor Rutgers U CS cs.utexas.edu/users/djimenez (old)	JPEG 120x143 120x143	microarchitecture, branch prediction, compilers and microarchitectures dblp
Hai Jin	Professor Huazhong U, China hust.edu.cn/hjin	JPEG 128x139 128x139	computer architecture and cluster computing, parallel and distributed computing, high performance network storage systems and Parallel I/O, web and network security, fault tolerance, performance evaluation and benchmarking dblp
Lizy Kurian John	Professor U of Texas, Austin, ECE ece.utexas.edu/~ljohn	GIF 49x58 49x58	processor architecture, workload characterization, native signal processing, compilers for innovative architectures dblp
Eric E. Johnson	Professor New Mexico State U atanasoff.nmsu.edu/ejohnson/ejohnson.html	JPEG 155x208 155x208	architectures for parallel and distributed computing, computer performance evaluation, simulation, mobile computing/wireless networks, hf radio networks, cryptography, network security dblp
Richard Johnson	Hewlett-Packard (old) trimaran.org/car_group/richard_johnson.html (old)	GIF 95x138 95x138	predication, dataflow-analysis, compilers dblp
Ross Johnson	IBM cs.wisc.edu/~galileo/ross/ross.html	?	AS/400, shared memory multiprocessors
Teresa L. Johnson	Hewlett-Packard Corporation crhc.uiuc.edu/IMPACT/people/graduated/Teresa_Johnson.html (old)	JPEG 118x159 118x159	cache performance, cache management dblp
Alex K. Jones	Professor U of Pittsburgh, ECE engr.pitt.edu/electrical/people/jones_alex.html	JPEG 135x135 135x135	high-level synthesis dblp
Mark T. Jones	Professor Virginia Tech, EE ecpe.vt.edu/faculty/mtjones.html	JPEG 85x105 85x105	high-performance computation, parallel and configurable computing, networks of embedded systems, distributed wireless sensor networks, distributed decision support systems, computational fabrics, numerical simulation, parallel algorithms dblp
Neil D. Jones	Professor DIKU, U of Copenhagen, Denmark diku.dk/users/neil	JPEG 216x206 216x206	programming languages, compilers, theory of computation dblp
Simon L. Peyton Jones	Microsoft Research research.microsoft.com/~simonpj	GIF 117x147 117x147	the Haskell Glasgow compiler, functional programming languages dblp
Norman P. Jouppi	Hewlett-Packard WRL wwww.hpl.hp.com/about/bios/norman_jouppi.html	JPEG 120x160 120x160	telepresence, graphics, CACTI, memory systems dblp
Roy D. C. Ju	Intel MRL intel.com/research/mrl/people/ju_roy.htm	JPEG 77x98 77x98	compiler optimization, program analysis, computer architecture, and parallel processing dblp
Ben H. H. Juurlink	Professor Delft U, Netherlands ce.et.tudelft.nl/~benj	JPEG 257x375 257x375	application-specific ISA extensions, multiple-issue processors, low-power techniques, hierarchical memory systems, parallel algorithms/architectures/programming/cost models dblp
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M. Frans Kaashoek	Professor MIT pdos.lcs.mit.edu/~kaashoek	GIF 152x191 152x191	Click modular router, Exokernel, tick-C, Amoeba/Orca dblp
Péter Kacsuk	head of the Parallel and Distributed Systems Laboratory Computer and Automation Research Institute of the Hungarian Academy of Sciences ultra10.lpds.sztaki.hu/staff/kacsuk_peter/sajat_honlap	JPEG 139x181 139x181	paralel logic programming, parallel computer architectures, parallel software engineering, Grid tools dblp
David R. Kaeli	Professor Northeastern U, ECE ece.neu.edu/faculty/kaeli.html	JPEG 156x227 156x227	branch prediction, I/O workload characterization, memory hierachy design, object-oriented code performance, 3-D VLSI design, compiler back-ends, trace-driven simulation dblp
Alain Kägi	Researcher Intel Microprocessor Research Labs intel.com/research/mrl/people/kagi_a.htm	JPEG 78x101 78x101	memory bandwith, optimized synchronization dblp
Krishnan Kailas	research staff IBM T. J. Watson e-kailas.net	?	low-power embedded architectures and DSP, microarchitecture and compilation for Clustered ILP processors dblp
Samuel N. Kamin	Professor U of Illinois at Urbana-Champaign, CS www-sal.cs.uiuc.edu/~kamin	JPEG 130x150 130x150	programming languages, software components, functional programming applied to scientific computation, denotational semantics, program specification and verification, domain-specific languages dblp
Mahmut Taylan Kandemir	Professor Penn State U cse.psu.edu/~kandemir	JPEG 70x80 70x80	embedded systems, optimizing compilers, power-aware computing, multi-dimensional databases dblp
Russell Kao	senior staff engineer Sun Research research.sun.com/people/rkao	JPEG 100x129 100x129	computer architecture, CAD, HP-PA, mixed switch-level/circuit level simulation dblp
Wolfgang Karl	Professor Muenchen Technical U, Germany wwwbode.cs.tum.edu/~karlw	GIF 149x195 149x195	computer architecture, microprocessors, computer and systems design, parallel and distributed systems, DSM, scalable coherent interface, fault tolerance, high availability, hot-swap, cache architectures, reconfigurable computing dblp
Hironori Kasahara	Professor Waseda U, Tokio, Japan kasahara.elec.waseda.ac.jp/kasahara.en.html	GIF 81x102 81x102	supercomputing, multiprocessor architectures, scheduling algorithms, parallelizing compilers, electronic circuit simulation dblp
Daniel Kästner	Senior Software Engineer AbsInt GmbH rw4.cs.uni-sb.de/~kaestner	JPEG 79x115 79x115	embedded systems, retargetable compiler construction, code generation and optimization, generative programming, Java, integer linear programming, program analysis, scheduling, document processing dblp
Ryan Kastner	Professor UC Santa Barbara ECE ece.ucsb.edu/~kastner	JPEG 89x103 89x103	embedded systems, reconfigurable computing, compilers, sensor networks dblp
Manolis G. H. Katevenis	Professor U of Crete, Grece archvlsi.ics.forth.gr/~kateveni	JPEG 133x170 133x170	packet switch architecture, high-speed networks, computer architecture, VLSI dblp
Vinod Kathail	R&D Program Manager Hewlett-Packard trimaran.org/car_group/vinod_kathail.html (old)	GIF 99x132 99x132	Trimaran, PICO, EPIC, Elcor dblp
Srinivas Katkoori	Professor U of South Florida vcapp.csee.usf.edu/~katkoori	JPEG 91x114 91x114	high level synthesis, low power synthesis, VLSI CAD for deep sub-micron regime, reconfigurable computing for space applications dblp
Joost-Pieter Katoen	Professor RWTH Aachen University, Germany www-i2.informatik.rwth-aachen.de/~katoen	JPEG 168x208 168x208	semantics, probabilistic verification, software verification, process algebra, formal specification dblp
Randy H. Katz	Professor UC Berkeley, CS cs.berkeley.edu/~randy	JPEG 194x269 194x269	network computing, communications-oriented service architectures dblp
Alireza Kaviani	Xilinx Research eecg.toronto.edu/~kaviani (old)	GIF 134x169 134x169	FPGA design dblp
Stefanos Kaxiras	Professor U of Patras, Greece cs.wisc.edu/~kaxiras	JPEG 95x121 95x121	SMP, cache decay, Datascalar dblp
Tom Kean	Director Algotronix Ltd. algotronix.com/people/tom	?	Xilinx XC6200 FPGA architecture, reconfigurable computing dblp
Stephen W. Keckler	Professor U of Texas, Austin, CS cs.utexas.edu/users/skeckler	JPEG 239x334 239x334	M-Machine, VLSI circuit design dblp
Gershon Kedem	Professor Duke U, CS kedem.cs.duke.edu	GIF 73x91 73x91	high performance memory systems dblp
Diana Keen	Professor Cal Poly csc.calpoly.edu/~dkeen	JPEG 229x279 229x279	computer architecture, compilers, intelligent memory dblp
Robert M. Keller	Professor Harvey Mudd College cs.hmc.edu/~keller	JPEG 182x224 182x224	programming languages: functional/parallel/real-time/logic, genetic programming dblp
Paul H. J. Kelly	Reader Imperial College of Science, Technology and Medicine, London, UK doc.ic.ac.uk/~phjk	GIF 186x257 186x257	computer systems issues underlying performance, performance evaluation / modelling / prediction, languages, compilers and operating systems for parallel computing dblp
Ken Kennedy	Professor Rice U, CS cs.rice.edu/~ken	GIF 207x236 207x236	vectorization, ParaScope, HPF, HPC dblp
Brian W. Kernighan	professor Princeton U, CS cs.princeton.edu/~bwk	JPEG 259x324 259x324	C, programming, AWK, AMPL dblp
Christoph W. Keßler	Professor Linkoping U, Sweden ida.liu.se/~chrke/	JPEG 136x196 136x196	parallel computing, compilers for instruction-level parallel and embedded processors, automatic parallelization dblp
Richard E. Kessler	Hewlett-Packard Research	?	processor caches, performance evaluation dblp
Kurt Keutzer	Professor UC Berkeley, EE www-cad.eecs.berkeley.edu/~keutzer	JPEG 167x198 167x198	MESCAL, embedded processor compilation, logic synthesis, test and timing verification, BACPAC dblp
Tom Kilburn	Professor (deceased) U of Manchester, UK computer50.org/mark1/kilburn.html Eckert-Mauchly (1981) award	JPEG 239x297 239x297	Mark1, MUSE/Atlas, MU5 dblp
Earl Killian	Chief Architect Tensilica killian.com/earl	JPEG 86x97 86x97	Pixie, processor architecture, MIPS, finger, SMTP dblp
Eun Jung Kim	Professor Texas A&M U, CS faculty.cs.tamu.edu/ejkim	GIF 139x168 139x168	computer architecture, power efficient systems, parallel/distributed systems, computer networks, cluster computing, QoS support in cluster networks and Internet, performance evaluation, fault-tolerant computing dblp
Shin-Dug Kim	Professor Yonsei U, Korea supercom.yonsei.ac.kr/~sdkim	GIF 119x149 119x149	advanced computer architectures, parallel processing systems, memory system design, heterogeneous Web computing, agent based Internet computing dblp
Taewhan Kim	Professor KAIST, Korea vlsisyn.kaist.ac.kr/~tkim	JPEG 316x415 316x415	embedded system design, architecture-level synthesis for system-on-chip, logic-level synthesis, high-level synhesis, routing for FPGAs dblp
David Kinniment	Professor U of Newcastle upon Tyne EE, UK staff.ncl.ac.uk/david.kinniment/	JPEG 346x445 346x445	synchronization, arbitration, metastability, asynchronous design, computer systems and microelectronics education dblp
Michael Kishinevsky	Strategic CAD Labs, Intel intel.com/research/people/bios/kishinevsky_m.htm	JPEG 70x78 70x78	high-level and asynchronous design, reactive systems, theory of concurrency dblp
Artur Klauser	Intel, VSSAD cs.colorado.edu/~klauser (old)	GIF 100x137 100x137	ILP, computer architecture and microarchitecture, compiler optimizations, operating systems, distributed and parallel systems, high-performance computing, multipath execution dblp
Tom Knight	Professor MIT ai.mit.edu/people/tk/tk.html	GIF 212x240 212x240	microbial engineering, reversible and low energy computing, VLSI microdisplays, Abacus (SIMD), transit, transactional execution of programs dblp
Jens Knoop	Professor U of Viena, Austria complang.tuwien.ac.at/knoop	GIF 65x82 65x82	lazy code motion, programming languages and compilers, formal methods, program analysis/verification/optimisation/tools, Internet dblp
Donald E. Knuth	Professor (emeritus) Stanford U, CS www-cs-faculty.stanford.edu/~knuth Turing (1974) award, National Medal of Science (1979)	GIF 139x172 139x172	parsing, Algol 60, profiling, TeX, algorithms dblp
Seok-Bum Ko	Professor U of Saskatchewan EE, Canada engr.usask.ca/~sek867	JPEG 231x301 231x301	FPGA, microprocessors dblp
Peter M. Kogge	Professor Notre Dame U nd.edu/~kogge	JPEG 102x146 102x146	massively parallel processing architectures, advanced VLSI technology and architectures, parallel algorithms and applications, processing in memory dblp
Cheng-Kok Koh	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~chengkok/	JPEG 301x355 301x355	layout-driven synthesis, interconnect-driven floorplanning and placement, global routing, clock synthesis, reduced-order modeling, power-supply network analysis and synthesis, very-high performance circuit design and synthesis dblp
Philip Koopman	Professor Carnegie Mellon U, ECE ece.cmu.edu/~koopman	JPEG 174x241 174x241	Ballista, embedded Computing, stack machines, Forth dblp
David M. Koppelman	Professor Louisiana State U ece.lsu.edu/koppel	?	interconnection networks, multiprocessors dblp
Israel Koren	Professor U of Massachusetts, Amherst ecs.umass.edu/ece/koren	JPEG 127x176 127x176	VLSI yield, CAD for yield estimation and reliability, fault tolerance in real-time systems, computer arithmetic dblp
Nectarios G. Koziris	Professor National Technical U of Athens, Greece cslab.ece.ntua.gr/~nkoziris	JPEG 170x211 170x211	parallel processing, parallel architectures, distributed systems, computer architecture dblp
Christoforos E. Kozyrakis	Professor Stanford U csl.stanford.edu/~christos	JPEG 222x342 222x342	microprocessor architecture and design, IRAM dblp
Andreas Krall	Professor Technische U Wien, Austria complang.tuwien.ac.at/andi/home.html	JPEG 205x265 205x265	object oriented languages, compiler back ends and computer architecture, logic programming, compilation for embedded processors dblp
Ulrich Kremer	Professor Rutgers U, CS athos.rutgers.edu/~uli	GIF 125x155 125x155	power and energy management, distributed embedded systems, compilation, data layout, performance prediction models dblp
Chandra Krintz	Professor UC Santa Barbara, CS cs.ucsb.edu/~ckrintz	JPEG 145x171 145x171	adaptive compilation, mobile Java code dblp
Daniel Kroening	postdoc Carnegie Mellon U kroening.com	JPEG 88x105 88x105	computer architecture, formal verification dblp
John D. Kubiatowicz	Professor UC Berkeley, CS cs.berkeley.edu/~kubitron	JPEG 197x276 197x276	IRAM, Oceanstore, Alewife, quantum computers dblp
William J. Kubitz	Professor (emeritus) U of Illinois at Urbana-Champaign, CS cs.uiuc.edu/people/faculty/kubitz.html	JPEG 109x131 109x131	VLSI physical design, computer graphics, converged media, mobile/wireless dblp
David J. Kuck	Chairman Kuck and Associates, Inc Eckert-Mauchly (1993) award, Charles Babbage award	GIF 151x174 151x174	parallel architectures, scientific computation, paralellizing compilers, Parafrase, KAP, KAI dblp
Philip J. Kuekes	Hewlett-Packard Labs hpl.hp.com/research/qsr/staff/kuekes.html	JPEG 153x192 153x192	Teramac, systolic computation dblp
Sanjeev Kumar	Computer Architect Researcher Intel MRL intel.com/research/people/bios/kumar_s.htm	JPEG 777x1167 777x1167	computer architecture, software systems dblp
H. T. Kung	Professor Harvard U eecs.harvard.edu/~htk	JPEG 131x153 131x153	networking, systolic arrays, parallel computing dblp
Fadi J. Kurdahi	Professor UC Irvine eng.uci.edu/faculty/kurdahi/fadi.html	GIF 118x145 118x145	high-level synthesis, estimation and design methodology of large scale systems dblp
Jeffrey Kuskin	Atheros Communications www-flash.stanford.edu/~jsk (old)	?	Stanford FLASH multiprocessor dblp
Bradley C. Kuszmaul	Senior Research Scientist Supercomputing Technologies Group MIT bradley.csail.mit.edu/~bradley	JPEG 68x75 68x75	CM-5, Ultrascalar, computer chess (StarTech and *Socrates), Cilk dblp
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Konrad Lai	Manager Intel Hillsboro Microarchitecture Labs intel.com/research/people/bios/lai_k.htm	?	microprocessor/memory/system architecture dblp
Monica S. Lam	Professor Stanford U suif.stanford.edu/~lam	GIF 95x111 95x111	SUIF, software pipelining, automatic parallelization, compilers dblp
Leslie Lamport	Microsoft Research lamport.org	GIF 150x200 150x200	Temporal Logic of Actions (TLA), Lamport clocks, Latex, parallel computation, metastability in asynchronous systems, formal methods, Byzantine agreement dblp
Butler W. Lampson	Microsoft Research research.microsoft.com/lampson	GIF 212x274 212x274	computer architecture, local area networks, raster printers, page description languages, operating systems, remote procedure call, programming languages and semantics, fault-tolerant computing, transaction processing, computer security, Alto personal distributed computing system, Xerox 9700 laser printer, two-phase commit protocol dblp
Anders Landin	Sun Microsystems sics.se/~landin (old)	GIF 115x152 115x152	multiprocessor architecture, memory systems, cache coherence, COMA, shared-memory application behaviour, architecture evaluation techniques, multiprocessor simulation dblp
Tomas Lang	Professor UC Irvine ece.uci.edu/faculty/lang.html	?	hardware for arithmetic dblp
Josep-Lluis Larriba-Pey	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/larri	?	software trace cache, branch prediction, performance of numerical algorithms dblp
James R. Larus	senior researcher Microsoft Research research.microsoft.com/~larus	GIF 103x119 103x119	program measurement, fine-grain shared memory, Wisconsin Wind Tunnel, SPIM, PP, QPT, EEL, path profiling dblp
Rudy Lauwereins	Professor U of Leuven, Belgium lesbos.esat.kuleuven.ac.be/dpt_people/person.php3?id=3	JPEG 85x107 85x107	embedded systems design, architectures/methods/tools for smart networked devices dblp
Luciano Lavagno	Professor Politecnico di Torino/Cadence, Italy polimage.polito.it/~lavagno	GIF 143x196 143x196	asynchronous circuit design and testing, hardware/software co-design of embedded systems dblp
Daniel M. Lavery	Intel Corporation	GIF 57x76 57x76	compilation for Itanium dblp
Edward D. Lazowska	Professor U of Washington, Seattle, CS cs.washington.edu/people/faculty/lazowska	JPEG 214x280 214x280	design/implementation/analysis of high-performance computing and communication systems dblp
Gary T. Leavens	Professor Iowa State U CS cs.iastate.edu/~leavens	GIF 213x270 213x270	multiple dispatch, multijava, formal methods (JML) dblp
Alvin R. Lebeck	Professor Duke U, CS cs.duke.edu/~alvy	GIF 118x135 118x135	computer systems, memory systems, energy-efficient computing, fast memory simulation, ICE, CURIOUS dblp
Ben Lee	Professor Oregon State U, ECE hubbard.ece.orst.edu/~benl	JPEG 400x505 400x505	software and architectural support for multithreading dblp
Corinna G. Lee	ATI Technologies eecg.utoronto.ca/~corinna (old)	GIF 162x222 162x222	UTDSP benchmark suite, performance of 3D graphics chips dblp
Edward A. Lee	Professor UC Berkeley, ECE ptolemy.eecs.berkeley.edu/~eal	GIF 141x166 141x166	Ptolemy, DSP, embedded systems dblp
Gyungho Lee	Professor University of Illinois at Chicago, ECE ece.uic.edu/People/lee.htm	GIF 97x119 97x119	DICE: cache-only memory multiprocessor, access-region cache: scalable memory pipeline, Amanita: system hardening, cache for embedded applications dblp
Hsien-Hsin Sean Lee	Professor Georgia Tech, ECE ece.gatech.edu/~leehs	JPEG 106x119 106x119	microarchitecture, compilers dblp
Jaejin Lee	Professor Michigan State U cse.msu.edu/~jlee/	JPEG 107x129 107x129	compilers, programming languages, HPC, memory consistency, processor-in-memory dblp
John A. N. Lee	Professor Virginia Tech, CS ei.cs.vt.edu/~janlee/Janlee.html	GIF 80x94 80x94	programming languages, compiler design, industry standards, software engineering, history of computing, computer ethics dblp
Peter Lee	Professor Carnegie Mellon U cs.cmu.edu/~petel	JPEG 180x248 180x248	design/implementation/foundations of programming languages, language-based computer security, code certification and proof-carrying code, functional programming, formal semantics, type theory dblp
Ruby B. Lee	Professor Princeton U, EE ee.princeton.edu/~rblee	JPEG 285x378 285x378	multimedia ISA, media processors and microarchitecture, secure information processing, processor architecture dblp
Sang-Jeong Lee	Professor Soonchunhyang U, Asan, Korea sjlee.sch.ac.kr/Default_eng.htm	GIF 82x102 82x102	ILP, optimizing compilers, value prediction dblp
Thomas H. Lee	Professor Stanford U, ECE www-smirc.stanford.edu/people.html	JPEG 79x101 79x101	gigahertz-speed wireline, wireless integrated circuits, high-speed analog circuitry dblp
Miriam Leeser	Professor Northeastern U ECE ece.neu.edu/faculty/leeser.html	?	FPGA design and applications, Computer Arithmetic, Hardware/Software interfacing dblp
Charles Lefurgy	research staff member IBM Austin research.ibm.com/people/l/lefurgy	JPEG 64x77 64x77	low energy computing, code compression dblp
K. Rustan M. Leino	Microsoft Research research.microsoft.com/~leino	GIF 128x151 128x151	programming tools, ESC/Java dblp
Charles E. Leiserson	Professor MIT supertech.lcs.mit.edu/~cel	JPEG 168x209 168x209	Cilk, retiming, algorithms, supercomputing, interconnection networks, parallel computation dblp
Guy G. Lemieux	Professor U of British Columbia ECE, Canada ece.ubc.ca/~lemieux	JPEG 176x237 176x237	multiprocessors, FPGAs dblp
Philip H. W. Leong	Professor Chinese University of Hong Kong cse.cuhk.edu.hk/~phwl	JPEG 54x77 54x77	reconfigurable computing, digital systems, parallel computing, cryptography, signal processing dblp
Xavier Leroy	Senior Researcher INRIA, France cristal.inria.fr/~xleroy	JPEG 144x196 144x196	type systems, module systems and static analyses, Ocaml, Linux threads dblp
Rainer Leupers	Professor Technische U Aachen, Germany iss.rwth-aachen.de/1_institut/dok/leupers.htm	GIF 158x223 158x223	embedded software tools, compilers for DSP and VLIW and network processors, code optimization, retargetable compilation, processor architecture dblp
Benjamin A. Levine	Professor U of Pittsburgh, ECE engr.pitt.edu/electrical/people/levine_benjamin.html	JPEG 143x176 143x176	reconfigurable computing, high-level synthesis dblp
Steven P. Levitan	Professor U of Pittsburgh, EE kona.ee.pitt.edu/steve	JPEG 188x290 188x290	CAD for free space optoelectronic, optoelectronic computing systems, VHDL simulation and synthesis, timing verification, design frameworks, VLSI architectures, parallel algorithm design dblp
Henry M. Levy	Professor U of Washington Seattle, CS cs.washington.edu/homes/levy	GIF 161x237 161x237	SMT, operating systems, Web dblp
David Lewis	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~lewis	JPEG 123x157 123x157	computer arithmetic, VLSI design, Transmogrifier, hierarchical FPGA architectures dblp
E. Christopher Lewis	Professor U of Pennsylvania cis.upenn.edu/~eclewis	JPEG 100x145 100x145	compilers and programming languages, computer architecture, programming systems for scalable parallel machines dblp
Kai Li	Professor Princeton U, CS cs.princeton.edu/~li	GIF 141x168 141x168	PRISM, SHRIMP, extensible router, scalable I/O dblp
Zhiyuan Li	Professor Purdue U, CS cs.purdue.edu/people/li	JPEG 70x96 70x96	optimizing compilers, interface between compilers and OS, performance evaluation of concurrent systems dblp
David J. Lilja	Professor U of Minesotta, EE www-mount.ee.umn.edu/~lilja/lilja.html	GIF 91x131 91x131	high-performance computer architecture, parallel processing, computer systems performance analysis, exploiting hardware-software interactions dblp
Sung Kyu Lim	Professor Georgia Tech, ECE users.ece.gatech.edu/~limsk	JPEG 272x338 272x338	physical design automation algorithms and tools for 3D circuits and packages, quantum circuits, FPGA/FPCA/FPAA based reconfigurable systems dblp
Calvin Lin	Professor U of Texas, Austin, CS cs.utexas.edu/users/lin	JPEG 68x87 68x87	compilers and languages, parallelism and scientific computing dblp
Christoph Lindemann	Professor Dortmund U, Germany rul-www.cs.uni-dortmund.de/~Lindemann/main.html	JPEG 213x273 213x273	Petri nets, performance evaluation dblp
Daniel T. Ling	Corporate Vice President Microsoft Corp. microsoft.com/presspass/exec/ling/default.asp	JPEG 93x111 93x111	user interfaces, computer graphics, video RAM, IBM America dblp
Dimitris Lioupis	Professor U of Patras, Greece aiolos.cti.gr/~lioupis	JPEG 175x217 175x217	caches, microprocessor design, multimedia architectures dblp
Mikko H. Lipasti	Professor U of Wisconsin-Madison, ECE ece.wisc.edu/~mikko	GIF 128x161 128x161	value prediction, computer architecture, ILP, compiler optimization, runtime systems, operating systems dblp
G. Jack Lipovski	Professor U of Texas at Austin, ECE engr.utexas.edu/news/facstaff/pages/lipovski.cfm	JPEG 393x554 393x554	artificial intelligence, computer architectures, microcomputers dblp
Dake Liu	Professor Linkoping U, Sweden isy.liu.se/~dake	JPEG 457x570 457x570	system on chip integration, Application Specific Instruction set Processors (ASIP), DSP processors and accelerators, communication ASICs dblp
Yanhong Annie Liu	Professor State U of NY at Stony Brook, CS cs.sunysb.edu/~liu	GIF 158x175 158x175	programming languages, compilers and software systems, program analysis and transformation for incremental/parallel/concurrent computation, optimizing compilers dblp
Josep Llosa	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/josepll	?	hardware and compiler support for ILP dblp
Jien-Chung Lo	Professor U of Rhode-Island ele.uri.edu/faculty/lo.html	JPEG 136x172 136x172	fault-tolerant computing, distributed networked computing, reliable logic circuit designs, VLSI testing dblp
Gabriel H. Loh	Professor Georgia Tech, CS cc.gatech.edu/~loh	JPEG 98x121 98x121	high-performance processor microarchitecture, branch prediction dblp
Ronald J. Lomax	Professor (emeritus) U of Michigan www-personal.engin.umich.edu/~rjl	JPEG 88x114 88x114	processor design dblp
Rita Loogen	Professor Philipps-Universitat, Marburg, Germany mathematik.uni-marburg.de/~loogen	JPEG 118x131 118x131	declarative parallel programming, integration of functional and logic programming languages, parallel implementation of functional languages dblp
P. Geoffrey Lowney	Director, Compiler and Architecture Advanced Development Intel Architecture Group intel.com/pressroom/kits/bios/plowney.htm	GIF 67x76 67x76	compilers for Alpha and Itanium, Multiflow, Spike dblp
Shih-Lien Lu	Intel MRL ece.orst.edu/~sllu (old)	GIF 108x129 108x129	counterflow pipelines, self-timed circuits and systems design, VLSI systems, computer arithmetic, computer architecture dblp
Yung-Hsiang Lu	Professor Purdue U, ECE ece.purdue.edu/~yunglu	GIF 64x74 64x74	energy-efficient and low-power systems, operating systems, wireless applications, reconfigurable architectures, VLSI design automation, embedded systems dblp
David Luick	IBM Rochester	?	VLIW
Chi-Keung Luk	Intel cs.cmu.edu/~luk (old)	JPEG 166x197 166x197	data prefetch for pointer code dblp
Wayne Luk	Senior lecturer Imperial College, London, UK doc.ic.ac.uk/~wl	GIF 75x89 75x89	run-time reconfigurable architectures, library-based compilation techniques dblp
Steven Lumetta	Professor U of Illinois Urbana-Champaign, ECE crhc.uiuc.edu/~steve	JPEG 129x188 129x188	high-performance networking and computing, hierarchical systems, parallel runtime software dblp
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Enrico Macii	Professor Politecnico di Torino, Italy eda.polito.it/enrico.html	?	CAD of digital integrated circuits and systems, logic synthesis/optimization/testing/formal verification, power estimation and optimization dblp
Kenneth M. Mackenzie	Adjunct Professor Georgia Tech U/Reservoir Labs cc.gatech.edu/~kenmac	JPEG 64x75 64x75	Fugu, Alewife, soft architectures, active system-area networks dblp
David B. MacQueen	Professor U of Chicago cs.uchicago.edu/people/dbm	GIF 113x146 113x146	programming language design/definition/implementation, type and module systems, SML/NJ dblp
Tara M. Madhyastha	Professor UC Santa Cruz cse.ucsc.edu/~tara	GIF 190x233 190x233	high-bandwidth I/O interfaces, automatic performance characterization and adaptation dblp
Vijay K. Madisetti	Professor Georgia Tech, ECE users.ece.gatech.edu/~vkm/home.html	JPEG 80x100 80x100	DSP, rapid prototyping, signal processors, VLSI CAD dblp
Bruce M. Maggs	Professor Carnegie Mellon U, CS cs.cmu.edu/~bmm	GIF 139x183 139x183	interconnection networks, parallels algorithms dblp
Nihar R. Mahapatra	Professor State U of New York at Bufallo cse.buffalo.edu/~mahapatr	JPEG 225x314 225x314	computer architecture, parallel processing, VLSI, fault tolerance dblp
Rabi N. Mahapatra	Professor Texas A&M U, CS cs.tamu.edu/faculty/rabi	JPEG 97x127 97x127	parallel and distributed computing, computer architecture, embedded system codesign dblp
Scott A. Mahlke	U of Michigan eecs.umich.edu/~mahlke	GIF 103x128 103x128	Trimaran, Elcor, EPIC, application-specific processor design, compilers, computer architecture, high-level synthesis dblp
Wai-Kei Mak	Professor National Tsing Hua U, Taiwan cs.nthu.edu.tw/~wkmak	JPEG 102x128 102x128	VLSI CAD, discrete optimization, combinatorial optimization, computer architecture dblp
Miroslaw Malek	Professor Humboldt U Berlin, Germany informatik.hu-berlin.de/~malek	GIF 106x130 106x130	high-performance responsive computing, parallel architectures, real-time systems, networks, fault tolerance dblp
Sharad Malik	Professor Princeton U, EE ee.princeton.edu/~sharad/	GIF 88x112 88x112	CAD, Electronic Design Automation, design tools for embedded systems, hardware-software integration, digital circuit theory, synthesis and verification of digital systems dblp
Wojciech P. Maly	Professor Carnegie Mellon U, ECE ece.cmu.edu/~maly	GIF 248x312 248x312	VLSI design testing and manufacturing dblp
William H. Mangione-Smith	Professor UC Los Angeles icsl.ucla.edu/~billms	GIF 116x158 116x158	configurable computing systems, low power processor and system design, multimedia and communications processing, instruction-level parallelism, Mediabench dblp
Rajit Manohar	Professor Cornell U, ECE vlsi.cornell.edu/~rajit	GIF 81x105 81x105	asynchronous VLSI design, low energy design, architecture, concurrency, formal methods, programming language semantics, information theory dblp
Elias S. Manolakos	Professor Northeastern U, ECE cdsp.neu.edu/info/faculty/manolakos/manolakos.html	GIF 75x97 75x97	high performance computing, synthesis of parallel algorithms and architectures, pattern recognition and neural networks dblp
Panagiotis Manolios	Professor Georgia Institute of Technology cc.gatech.edu/~manolios	JPEG 276x369 276x369	formal verification, theorem proving, model checking, abstraction, algorithms dblp
Olivier Maquelin	postdoc McGill U, Montreal, Canada cs.mcgill.ca/~maquelin (old)	?	multithreaded systems, EARTH dblp
Diana Marculescu	Professor Carnegie Mellon U, ECE ece.cmu.edu/~dianam	JPEG 189x196 189x196	energy-aware computing, low power CAD dblp
Radu Marculescu	Professor Carnegie Mellon U, ECE ece.cmu.edu/~radum	JPEG 69x92 69x92	embedded systems, low-power CAD dblp
Malgorzata Marek-Sadowska	Professor U of California at Santa Barbara, ECE ece.ucsb.edu/Faculty/Marek-Sadowska/default.html	GIF 139x169 139x169	VAD for layout and logic synthesis, simulation of nonlinear circuits, timing verification dblp
Darko Marinov	Professor U of Illinois at Urbana-Champaign CS cag.lcs.mit.edu/~marinov	JPEG 253x322 253x322	specification languages, checking code conformance, compilers, correctness of analyses and optimizations dblp
Evangelos P. Markatos	Professor U of Crete, Grece ics.forth.gr/~markatos	GIF 87x89 87x89	systems software for large scale multiprocessros, Psyche multiprocessor OS dblp
Igor L. Markov	Professor U of Michigan eecs.umich.edu/~imarkov	JPEG 79x93 79x93	design of integrated circuits, quantum computing dblp
Marco Ajmone Marsan	Professor Politecnico di Torino, Italy www1.tlc.polito.it/ajmone	JPEG 62x74 62x74	high-speed telecommunication networks, wireless and all-optical networks, performance evaluation of data communication and computer systems, Markovian models, queuing networks, generalized stochastic Petri nets dblp
Alain J. Martin	Professor Caltech U, CS cs.caltech.edu/cspeople/faculty/martin_a.html	JPEG 72x109 72x109	asynchronous VLSI dblp
Milo M. K. Martin	Professor U of Pennsylvania cis.upenn.edu/~milom	JPEG 268x374 268x374	computer architecture, multiprocessors, memory coherence dblp
Jose F. Martinez	Professor Cornell U, ECE csl.cornell.edu/~martinez	JPEG 120x163 120x163	parallel computer architecture dblp
Margaret Martonosi	Professor Princeton U, EE ee.princeton.edu/~mrm	JPEG 57x72 57x72	cache-decay, cache-miss equations, reconfigurable hardware (SAT) dblp
Peter Marwedel	Professor U of Dortmund, Germany ls12-www.cs.uni-dortmund.de/~marwedel	JPEG 151x201 151x201	compilers for embedded processors, embedded software, high-level synthesis, test program generation for processors dblp
Peter M. Maurer	Professor U of South Florida csee.usf.edu/~maurer	JPEG 105x125 105x125	VLSI design automation, VLSI design, software testing, computer architecture, parallel processing, FHDL, DGL dblp
John D. McCalpin	Senior Scientist IBM, Austin home.austin.rr.com/mccalpin	JPEG 149x214 149x214	memory bandwidth, STREAM benchmark
Joel McCormack	Hewlett Packard WRL research.compaq.com/wrl/people/joel/bio.html	JPEG 114x139 114x139	computer graphics, CAD dblp
Scott McFarling	Microsoft Research research.microsoft.com/~smcfar	JPEG 75x75 75x75	profile-based optimization of memory performance, branch prediction dblp
Sally A. McKee	Professor Cornell U ECE csl.cornell.edu/~sam	JPEG 161x195 161x195	processor and memory systems architecture, embedded systems, compilers, operating systems, performance analysis techniques and tools, Impulse dblp
Nick McKeown	Professor Stanford U, EE klamath.stanford.edu/~nickm	GIF 127x171 127x171	Tiny Tera, packet switches dblp
Kathryn S. McKinley	Professor U of Texas, Austin, CS cs.utexas.edu/users/mckinley	JPEG 156x162 156x162	compilers, ParaScope dblp
Kenneth L. McMillan	Researcher Cadence Berkeley Labs www-cad.eecs.berkeley.edu/~kenmcmil	JPEG 112x151 112x151	formal verfication, symbolic model checking, SMV dblp
Carver A. Mead	Professor (emeritus)/Chairman Caltech U/Foveon foveon.com/about_executive.html Allen Newel (1997) award, von Neumann Medal	JPEG 98x139 98x139	semiconductors, physics of computation dblp
Eduard Mehofer	Professor U of Viena, Austria par.univie.ac.at/~mehofer	JPEG 304x415 304x415	optimising compilers, parallel and distributed computing, communication optimizations, feedback-directed compilation, grid computing dblp
Nagi N. Mekhiel	Professor Ryerson Polytechnic U, Canada ee.ryerson.ca/~nmekhiel	GIF 200x281 200x281	computer architecture and parallel processing, high performance memory systems, VLSI, performance evaluation
Waleed M. Meleis	Professor Northeastern U, ECE ece.neu.edu/faculty/meleis.html	JPEG 164x217 164x217	code scheduling dblp
Rami G. Melhem	Professor U of Pittsburgh, CS cs.pitt.edu/~melhem	GIF 94x118 94x118	fault-tolerant systems, optical networks, real-time parallel and distributed systems, power aware computing dblp
John M. Mellor-Crummey	Professor Rice U, CS cs.rice.edu/~johnmc	JPEG 137x178 137x178	software support for HCP, multiprocessor synchronization, parallel debugging, parallel operating systems, parallelizing compilers, compiler and run-time techniques for improving memory hierarchy performance dblp
Gokhan Memik	Professor Northwestern U ECE ece.northwestern.edu/~memik	JPEG 115x156 115x156	application-specific programmable processors, compilers, embedded systems, microarchitecture dblp
Oskar Mencer	Professor Imperial College, UK/Bell Labs, Lucent doc.ic.ac.uk/~oskar/	GIF 61x80 61x80	general computer architecture, custom computing, FPGAs, computer arithmetic, domain-specific compilers, low-power computing, CAD and VLSI dblp
Bilha Mendelson	Manager, Code optimization group IBM Research Lab, Haifa, Israel	JPEG 96x120 96x120	code optimization, compiler optimization, modern computer architecture dblp
Teresa H. Meng	Professor Stanford U, ECE dualist.stanford.edu/~thm	JPEG 396x484 396x484	low-power circuit and system design, video signal processing, wireless communications, circuit optimization, neural signal processing, computation architectures for future CMOS technology, Atheros Communications dblp
José Meseguer	Professor U of Illinois at Urbana-Champaign, CS formal.cs.uiuc.edu/meseguer/	JPEG 105x118 105x118	declarative languages, OBJ, Maude, formal specification and verification, concurrency theory, parallel software and architectures for declarative languages, logical foundations of computer science dblp
David G. Messerschmitt	Professor UC Berkeley, ECE eecs.berkeley.edu/~messer	GIF 112x168 112x168	technology/economy/business, DSP, networking, VLSI, signal processing dblp
David G. Meyer	Professor Purdue U, ECE digibowser.ecn.purdue.edu/dsl/meyer.html	JPEG 163x198 163x198	instructional multimedia, technology-based education, computer architecture and parallel processing, microprocessor system design and interfacing, electro-acoustics dblp
Dirk Meyer	senior vice president AMD corp. Maurice Wilkes (2003) award	JPEG 59x68 59x68	Athlon, Opteron, Alpha 21064, 21264
Maged M. Michael	IBM T. J. Watson cs.rochester.edu/u/michael (old)	GIF 91x113 91x113	distributed shared memory dblp
Pierre Michaud	Researcher IRISA, France irisa.fr/caps/people/michaud/index_fr.htm	JPEG 77x104 77x104	computer architecture dblp
Giovanni De Micheli	Professor Stanford U, ECE akebono.stanford.edu/users/nanni	GIF 125x160 125x160	CAD, digital circuits, hw/sw codesign, VLSI dblp
Samuel P. Midkiff	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~smidkiffw	JPEG 94x114 94x114	high performance compilers, programming environments and tools, compilation of explicitly parallel programs, utility of consistency models, compiling for safety and repeatability, Polaris, Numeric Java dblp
Robin Milner	Professor U of Cambridge, UK cl.cam.ac.uk/users/rm135 Turing (1991) award	GIF 164x231 164x231	LCF, ML, CCS dblp
Veljko M. Milutinovic	Professor U of Belgrade, Serbia, Yugoslavia galeb.etf.bg.ac.yu/~vm	JPEG 108x134 108x134	Internet, infrastructure for Electronic Business on Internet, SMP and DSM, VLSI, microprocessor architecture/design, FPGA, silicon compilation dblp
Jayadev Misra	Professor U of Texas, Austin, CS cs.utexas.edu/users/misra	JPEG 117x142 117x142	formal methods, specifications/designs of synchronous/asynchronous systems, UNITY dblp
Markus U. Mock	Professor U of Pittsburgh, CS cs.pitt.edu/~mock	JPEG 182x228 182x228	compilers and computer architecture, (run-time) program optimization, static and dynamic program analysis dblp
Adrian Moga	Sequent Computer Systems Inc usc.edu/dept/ceng/dubois/moga/moga.html (old)	GIF 119x150 119x150	DSM, hardware emulation dblp
Saraju P. Mohanty	Professor U of North Texas cs.unt.edu/~smohanty	JPEG 153x189 153x189	CAD for nanoscale VLSI, synthesis and optimization for low power, power-aware system design, VLSI architectures for security and DRM dblp
Aloysius K. Mok	Professor U of Texas at Austin cs.utexas.edu/users/mok	JPEG 148x178 148x178	fault-tolerant hard-real-time systems, system architecture, computer-aided system design tools, software engineering dblp
Dan I. Moldovan	Professor U Texas at Dallas utdallas.edu/~moldovan	JPEG 102x132 102x132	systolic processors, natural language processing, machine learning, artificial intelligence, parallel and distributed processing dblp
Charles E. Molnar	(deceased) U of Washington in St. Louis /www.cse.wustl.edu/history/molnar_c	GIF 325x425 325x425	asynchronous circuits, metastability, LINC, audio signals and neural responses, biomedical computing dblp
Burkhard Monien	Professor U Paderborn, Germany uni-paderborn.de/fachbereich/AG/monien/PERSONAL/bm.html	GIF 114x154 114x154	parallel computation, parallel architecture, scientific computing, interconnection networks dblp
Soo-Mook Moon	Professor Seoul National U, Korea ee.snu.ac.kr/english/faculty/moon-soomook.htm	JPEG 133x173 133x173	system software, microprocessor structure, superpipelining dblp
Oege de Moor	Professor Oxford U, UK web.comlab.ox.ac.uk/oucl/people/oege.demoor.html	GIF 174x241 174x241	intentional programming, transformation of Haskell programs, algebra of programming, predicate transformers, compositional logic programming, complexity and programming languages dblp
Gordon E. Moore	Chairman Emeritus of the Board Intel developer.intel.com/pressroom/kits/bios/moore.htm	JPEG 224x304 224x304	Moore's law, Intel dblp
J. Strother Moore	Professor U of Texas, Austin, CS cs.utexas.edu/users/moore	JPEG 55x76 55x76	theorem prooving, Boyer-Moore theorem prover, hardware and software verification, ACL2 dblp
Edward David Moreno	Professor U of Sao Paulo, Brazil lsi.usp.br/~edmoreno	JPEG 146x190 146x190	computer architecture, performance evaluation and analysis, Petri nets, computer networks, reconfigurable hardware dblp
Jaime H. Moreno	IBM T. J. Watson	?	processor architecture, ILP, embedded systems, systolic matrix computations dblp
Csaba Andras Moritz	Professor U of Massachusetts, Amherst ecs.umass.edu/ece/andras	JPEG 308x387 308x387	Cool-*: compiler-enabled power-aware microprocessor architecture, self-evolving software/hardware dblp
John Morris	Professor U of Western Australia ciips.ee.uwa.edu.au/~morris	JPEG 87x108 87x108	high performance parallel processors, reconfigurable processors, networks of workstations, fault-tolerant Cilk, Achilles high-bandwidth interconnect, asynchronous logic, software verification dblp
Andreas Moshovos	Professor U of Toronto, EE, Canada eecg.toronto.edu/~moshovos	JPEG 128x163 128x163	PACT, SHARPP, slice processors, memory dependence speculation dblp
J. Eliot B. Moss	Professor U of Massachusetts, Amherst www-osl.cs.umass.edu/~moss	GIF 109x146 109x146	programming language design and implementation, database and information retrieval systems, persistent object stores and persistent programming languages, memory management and garbage collection dblp
Todd C. Mowry	Professor Carnegie Mellon U, CS cs.cmu.edu/~tcm	JPEG 166x241 166x241	Thread-Level Data Speculation, Stampede, software prefetching dblp
Steven S. Muchnick		?	compilers dblp
Trevor N. Mudge	Professor U of Michigan eecs.umich.edu/~tnm	GIF 87x106 87x106	PowerAnalyzer, instruction stream compression, microprocessor verification, high performance computing dblp
Frank Mueller	Professor North Carolina State U moss.csc.ncsu.edu/~mueller	GIF 108x146 108x146	compilers, real-time systems, parallel and distributed systems dblp
Silvia M. Mueller	U des Saarlandes, Germany www-wjp.cs.uni-sb.de/~smueller	?	complexity and correctness of computer architectures, parallel architectures: design / modelling / performance, parallelization of algorithms, hardware support for multimedia dblp
Shubhendu S. Mukherjee	Hewlett Packard cs.wisc.edu/~shubu/shubu.html (old)	JPEG 153x207 153x207	network interfaces, coherence protocols dblp
Hans Mulder	Senior Principal Engineer Intel Research intel.com/research/people/bios/mulder_h.htm	JPEG 78x112 78x112	Itanium, distributed systems, ubiquitous computing dblp
Henk Muller	Reader U of Bristol, UK cs.bris.ac.uk/~henkm	GIF 157x195 157x195	data diffusion machine, trivial mobile software, PRISMA, DOOM dblp
Jean-Michel Muller	senior researcher Ecole Normale Superieure de Lyon, France ens-lyon.fr/~jmmuller	JPEG 321x438 321x438	algorithms and architectures for fast and/or accurate arithmetic, number systems, elementary functions, Cordic dblp
Markus Müller-Olm	Research assistant Dortmund U, Germany sunshine.cs.uni-dortmund.de/~mmo	JPEG 111x140 111x140	analysis and verification of programs and systems dblp
Kazuaki Murakami	Professor Kyushu U, Japan kasuga.csce.kyushu-u.ac.jp/~murakami	GIF 93x126 93x126	computer system architecture, parallel computing/processing, compiling for parallel architectures, performance evaluation, architecture/hardware modeling and optimization dblp
Saburo Muroga	Professor (emeritus) U of Illinois Urbana-Champaign, ECE cs.uiuc.edu/contacts/faculty/muroga.html	JPEG 130x150 130x150	CAD, Transduction, SYLON dblp
Chris J. Myers	Professor U of Utah, ECE shang.elen.utah.edu/~myers	JPEG 179x235 179x235	design methods and tools for VLSI systems, asynchronous circuit design, formal timing verification, design of analog decoders dblp
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David Nagle	Research Scientist Carnegie Mellon U, ECE ece.cmu.edu/~bassoon	GIF 68x80 68x80	Active storage, MEMS storage, NASD dblp
Walid A. Najjar	Professor UC Riverside, CS cs.ucr.edu/~najjar	JPEG 234x306 234x306	reconfigurable computing, Cameron, multithreaded and parallel architectures and compilation techniques, interconnection networks and router architectures, SA-C dblp
Farid N. Najm	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~najm	JPEG 221x292 221x292	CAD tool for low-power and reliable VLSI circuits, high-level power modeling and estimation, low-power design, reliability analysis and prediction, CAD for SOI circuits dblp
Ashwini K. Nanda	Manages, Scalable Server Architecture Group IBM T. J. Watson research.ibm.com/people/a/ashwini	?	computer architecture, shared memory system design and performance dblp
Lasse Natvig	Professor Norwegian U of Science and Technology, Norway idi.ntnu.no/~lasse	GIF 224x296 224x296	computer architecture, parallel algorithms, architectures and programming, theoretical models of parallel computation, simulation of computer systems dblp
George C. Necula	Professor UC Berkeley, CS cs.berkeley.edu/~necula	JPEG 150x200 150x200	Proof-Carrying Code (PCC), certifying compilation, translation validation dblp
Brent E. Nelson	Professor Brigham Young U, EE ee.byu.edu/faculty/nelson	JPEG 80x108 80x108	hardware design and CAD, reconfigurable computing, VLSI design, Teramac dblp
John von Neumann	(deceased) Princeton U nationalacademies.org/history/members/neumann.html	GIF 363x436 363x436	von Neumann architecture, stored program concept, reliability theory, logic design, self-reproducing automata dblp
Lionel M. Ni	Professor Michigan State U mcast.cps.msu.edu/ni	GIF 121x149 121x149	local network, VLSI design automation, parallel compilers, computer system performance evaluation, fault-tolerant computing, parallel machines, cut-through switch architecture dblp
Alexandru Nicolau	Professor UC Irvine ics.uci.edu/~nicolau	JPEG 298x381 298x381	paralellizing compilers, embedded systems dblp
Michael T. Niemier	Professor Georgia Tech, CS cc.gatech.edu/~mniemier	JPEG 95x95 95x95	computer architecture, quantum celular automata dblp
Rishiyur S. Nikhil	Sandburst Corporation	GIF 142x168 142x168	*T, P-RISC, multithreading, ASIC design in high-level languages dblp
David Notkin	Professor U of Washington Seattle, CS cs.washington.edu/homes/notkin/	GIF 137x192 137x192	dynamic detection of program invariants, symbolic model checking for software specifications, software engineering dblp
Andreas G. Nowatzyk	Professor Carnegie Mellon U, ECE cs.cmu.edu/~agn	GIF 100x138 100x138	single-chip multiprocessors, 3D cellular automata dblp
Steven M. Nowick	Professor Columbia U, CS cs.columbia.edu/~nowick	JPEG 137x165 137x165	asynchronous digital circuits, VLSI CAD, low-power and high-performance digital design, logic synthesis, formal hardware verification dblp
Jari Nurmi	Professor U of Tampere, Finland cs.tut.fi/~nurmi	JPEG 109x147 109x147	DSP, digital communication systems-on-chip dblp
Kristen Nygaard	(deceased) Oslo U, Norway ifi.uio.no/~kristen Turing (2001) award, von Neumann Medal (2001)	JPEG 208x264 208x264	Simula, object-oriented programming dblp
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Robert O'Callahan	Novell cs.cmu.edu/~roc (old)	JPEG 233x297 233x297	context-sensitive alias analysis using types, Mozilla, multithreaded program analysis, race detection dblp
Ciaran O'Donnell	Systems Software Consultant Joseph Media Tools, Santa Clara, CA josephmediatools.com/album1_003.htm	JPEG 76x90 76x90	compilers, architecture simulation dblp
David O'Hallaron	Professor Carnegie Mellon U, CS cs.cmu.edu/~droh	GIF 121x150 121x150	Quake, Warp, HPC, Fx dblp
John O'Leary	senior engineer Strategic CAD Labs, Intel	GIF 53x66 53x66	formal hardware verification and specification dblp
Stuart F. Oberman	Principal Engineer NVIDIA oberman.net	JPEG 51x64 51x64	floating-point division, computer arithmetic dblp
Martin Odersky	Professor Ecole Polytechnique Federale de Lausanne, Switzerland lampwww.epfl.ch/~odersky	JPEG 131x192 131x192	object-oriented and functional programming, Scala dblp
Vojin G. Oklobdzija	Professor UC Davis, ECE ece.ucdavis.edu/acsel	JPEG 150x191 150x191	high-speed digital circuits, VLSI arithmetic and development of fast structures, design for low-power, high-performance system architecture, design methodology for testability and reliability dblp
Ken Olsen	computerhistory.org/events/hall_of_fellows/olsen	JPEG 77x87 77x87	minicomputer, Digital Equipment Corp.
Kunle Olukotun	Professor Stanford U, CS ogun.stanford.edu/~kunle	GIF 363x444 363x444	Hydra, system-level design dblp
Amos Omondi	Professor Flinders U, Adelaide, Australia infoeng.flinders.edu.au/people/pages/omondi_amos	JPEG 64x81 64x81	computer architecture, multimedia processors, computer arithmetic dblp
Soner Önder	Professor Michigan Tech U, CS cs.mtu.edu/~soner	GIF 49x64 49x64	computer architecture, programming languages dblp
Tamiya Onodera	IBM Research Tokio trl.ibm.com/people/onodera	?	efficient implementation of object-oriented programming languages dblp
Alex Orailoglu	Professor UC San Diego, CS cs.ucsd.edu/users/alex	JPEG 110x127 110x127	Electronic Design Automation, VLSI testing, Synthesis of fault-tolerant ICs dblp
Mark Oskin	Professor U of Washington, Seattle, CS cs.washington.edu/homes/oskin	JPEG 145x207 145x207	computation cache, quantum computer architecture, active pages dblp
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David A. Padua	Professor U of Illinois Urbana-Champaign, CS polaris.cs.uiuc.edu/~padua	JPEG 130x150 130x150	computer architecture and systems, parallel computing, POLARIS dblp
Yunheung Paek	Professor Seoul National U ECE, Korea compiler.snu.ac.kr	JPEG 133x169 133x169	rapid ASIP prototyping, compiler optimizations for network processors, automatic parallelization PC clusters dblp
Ian Page	Reader Oxford U, UK doc.ic.ac.uk/~ipage	JPEG 127x155 127x155	Handel-C, hardware compilation dblp
Vijay S. Pai	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~vpai/	GIF 204x253 204x253	multiprocessors, high-performance system architecture dblp
Subbarao Palacharla	Desktop Platforms Group, Intel Corporation	GIF 61x84 61x84	complexity-effective superscalar dblp
Krishna V. Palem	Professor Georgia Tech U, ECE ece.gatech.edu/faculty/fac_profiles/bio.php?empno=504573	JPEG 74x89 74x89	adaptive hardware, compiler optimizations for ILP, embedded and fault-tolerant systems, parallel computing, programmable memory hierarchies, smart caches, real-time systems, string and pattern matching, Trimaran dblp
Jens Palsberg	Professor UC Los Angeles, CS cs.ucla.edu/~palsberg	JPEG 224x305 224x305	type inference for object-oriented software, interoperability of software systems, high assurance for embedded software, type-based analysis and applications dblp
David Z. Pan	Professor U of Texas at Austin ECE ece.utexas.edu/~dpan	JPEG 193x205 193x205	VLSI CAD, physical design, low power, design for manufacturability dblp
Dhabaleswar K. Panda	Professor Ohio State U cis.ohio-state.edu/~panda	GIF 84x99 84x99	parallel computer architecture, wormhole routing, interprocessor communication, DSM, HPC, clustered and heterogeneous systems, quality of service, resource management dblp
Santosh Pande	Professor Georgia Tech U, CS cc.gatech.edu/~santosh	JPEG 178x261 178x261	compiler optimizations for embedded and configurable systems dblp
Greg Papadopoulos	vice president, CTO Sun sun.com/aboutsun/media/ceo/mgt_papadopoulos.html	JPEG 134x172 134x172	scalable systems, multithreaded/dataflow processor architecture, functional and declarative languages, fault-tolerant computing dblp
Efstathios Papaefstathiou	Microsoft Research, Cambridge, UK research.microsoft.com/users/efp	JPEG 138x179 138x179	analytical and hybrid performance modeling methodologies and tools, parallel programming paradigms and development tools, software performance engineering, Indy dblp
Marios C. Papaefthymiou	Professor U of Michigan eecs.umich.edu/~marios	JPEG 88x115 88x115	computer system design, energy and timing, parallel and distributed computing dblp
Corina S. Pasareanu	NASA Ames ase.arc.nasa.gov/people/pcorina	JPEG 173x195 173x195	formal software verification, program abstraction, modular reasoning dblp
Nikolaos P. Paschalidis	Space Department, John Hopkins U	JPEG 430x550 430x550	analog digital microlectronics, sensors and microsystems for space instruments and spacecraft avionics, space physics
Janak H. Patel	Professor U of Illinois at Urbana-Champaign, ECE ece.uiuc.edu/faculty/faculty.asp?jhpatel	JPEG 132x185 132x185	computer architecture, testing and fault-tolerance dblp
Sanjay J. Patel	Professor U of Illinois Urbana-Champaign, ECE crhc.uiuc.edu/~sjp	JPEG 68x82 68x82	processor microarchitcture, computer architecture, high performance, reliable computer systems, trace cache dblp
Yale N. Patt	Professor U of Texas, Austin, ECE ece.utexas.edu/~patt Eckert-Mauchly (1996) award	JPEG 310x304 310x304	HPS, two-level branch prediction, computer architecture dblp
David A. Patterson	Professor UC Berkeley, CS cs.berkeley.edu/~pattrsn von Neumann Medal (2000)	JPEG 140x180 140x180	RISC, RAID dblp
Donald O. Pederson	(deceased) UC Berkeley berkeley.edu/news/media/releases/2005/01/05_donpederson.shtml	JPEG 149x207 149x207	SPICE dblp
Li-Shiuan Peh	Professor Princeton U, EE ee.princeton.edu/~peh	JPEG 92x109 92x109	interconnection networks dblp
Doron A. Peled	Professor University of Warwick, UK dcs.warwick.ac.uk/~doron	JPEG 89x101 89x101	concurrency theory, formal verification, formal specification, semantics of programming languages, model checking, finite automata, software testing, temporal logics, partial order methods, traces dblp
Ronald H. Perrott	Professor Queen's University Belfast, United Kingdom cs.qub.ac.uk/~R.Perrott	JPEG 170x225 170x225	Grid Computing, software engineering, design and implementation of parallel programming languages, high performance computing and support tools, Design/construction/analysis of algorithms dblp
Erez Petrank	Professor Israel Institute of Technology (Technion) cs.technion.ac.il/~erez	JPEG 91x135 91x135	cryptography, garbage collection, computational complexity dblp
Frank Pfenning	Professor Carnegie Mellon U, CS cs.cmu.edu/~fp	JPEG 233x310 233x310	programming languages, logic and type theory, logical frameworks, automated deduction dblp
Michael Philippsen	Professor U Erlangen-Nürnberg, Germany www2.informatik.uni-erlangen.de/~phlipp	JPEG 115x168 115x168	compilers for Java dblp
Christian Piguet	head of the ultra-low-power sector Centre Suisse d'Electronique et de Microtechnique	JPEG 152x195 152x195	very low-power microprocessors, low-power standard cell libraries, gated clock and low-power techniques, asynchronous design dblp
Lawrence T. Pileggi	Professor Carnegie Mellon U, ECE ece.cmu.edu/~pileggi	GIF 123x165 123x165	delay metrics, clock distribution and design, interconnects, timing analysis dblp
Keshav K. Pingali	Professor Cornell U, CS cs.cornell.edu/annual_report/pingali.htm	GIF 164x225 164x225	High Performance Computing, compilers, program analysis dblp
Timothy M. Pinkston	Professor U of Southern California usc.edu/dept/ceng/pinkston/people/pinkston.html	JPEG 76x88 76x88	high-performance interconnection networks for multiprocessors, performance analysis, optical interconnection networks, parallel processing dblp
Nikos P. Pitsianis	Professor Duke U, CS cs.duke.edu/~nikos	JPEG 162x228 162x228	numerical linear algebra and parallelization, symbolic and compiler optimization, FFTs, wavelets, simulation, high performance and scientific computing dblp
Marco Platzner	Professor ETH Zurich, Switzerland tik.ee.ethz.ch/~platzner	GIF 112x146 112x146	reconfigurable computing, hardware/software codesign, embedded systems dblp
Andrew R. Pleszkun	Professor U of Colorado, ECE ece-www.colorado.edu/faculty/pleszkun.html	GIF 122x162 122x162	computer architecture dblp
Dionisios N. Pnevmatikatos	Professor Technical U of Crete, Grece ics.forth.gr/~pnevmati	JPEG 104x139 104x139	VLSI design and implementation of processors and network switches, ILP processor architectures: instruction fetching/predicated execution/compilation techniques, systems design: memory/disk/clusters of workstations dblp
Amir Pnueli	Professor Weizmann Institute, Israel wisdom.weizmann.ac.il/~amir Turing (1996) award	GIF 143x183 143x183	formal verification dblp
Fred J. Pollack	Director Intel Microprocessor Research Labs developer.intel.com/pressroom/kits/bios/fpollack.htm	JPEG 100x130 100x130	Pentium Pro, i960, operating systems dblp
Constantine D. Polychronopoulos	Professor U of Illinois at Urbana-Champaign, ECE ece.uiuc.edu/faculty/faculty.asp?cdp	JPEG 72x100 72x100	compilers and operating systems, parallel and distributed computing, wireless networks and mobile computing dblp
Dmitry V. Ponomarev	Professor U of Binghampton CS cs.binghamton.edu/~dima/	JPEG 113x138 113x138	energy efficient design, high-end microprocessors dblp
Viktor Prasanna	Professor U of Southern California ceng.usc.edu/~prasanna	GIF 72x89 72x89	high performance computing, parallel and distributed systems, network computing, embedded systems dblp
Ian A. Pratt	Senior lecturer U of Cambridge Computer Laboratory, UK cl.cam.ac.uk/users/iap10	JPEG 136x172 136x172	computer architecture, networking, operating systems, Xen dblp
Milos Prvulovic	Professor Georgia Tech, CS cc.gatech.edu/~milos	JPEG 284x371 284x371	computer architecture, architectural support for programmability and productivity, fault tolerance and recovery, thread-level speculation dblp
William Pugh	Professor U of Maryland, CS cs.umd.edu/~pugh	JPEG 119x159 119x159	skip lists, Omega test, algorithms and data structures, automatic parallelization, dependence analysis, Java dblp
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Bin Qiu	Professor Monash U csse.monash.edu.au/research/avipac/njnf/staff_profiles/profile_bq.htm	JPEG 147x192 147x192	signal processing, network QoS and congestion control, network traffic modelling and prediction, communication electronics and computer architecture, video and image processing dblp
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Jan M. Rabaey	Professor UC Berkeley, EE bwrc.eecs.berkeley.edu/People/Faculty/jan	GIF 198x298 198x298	digital integrated circuits, low-power design dblp
Sriram K. Rajamani	Microsoft Research research.microsoft.com/~sriram	JPEG 235x293 235x293	model checking, static analyses, SLAM dblp
Ryan Rakvic	Intel ece.cmu.edu/~rnr (old)	?	memory hierarchy optimizations dblp
Umakishore Ramachandran	Professor Georgia Tech U, CS cc.gatech.edu/~rama	JPEG 259x326 259x326	Clouds, Beehive, Stampede dblp
G. Ramalingam	IBM T. J. Watson research.ibm.com/people/r/rama/	JPEG 130x157 130x157	static analysis, compilers dblp
C. V. Ramamoorthy	Professor (emeritus) UC Berkeley, CS cs.berkeley.edu/People/Faculty/Homepages/ramamoorthy.html	GIF 76x93 76x93	distributed systems, Petri nets, software engineering, databases dblp
J. Ramanujam	Professor Louisiana State U ece.lsu.edu/jxr	JPEG 151x187 151x187	compiler optimizations, embedded systems, low-power computing, high performance computing, hardware synthesis, configurable computing, computer architecture, operating systems, distributed systems dblp
Alex Ramirez	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/aramirez	JPEG 112x146 112x146	fetch engine performance, commercial workloads, compiler optimizations, binary translation, architecture simulation dblp
Norman Ramsey	Professor Harvard U eecs.harvard.edu/~nr	JPEG 85x90 85x90	C--, SLED, Zephyr, retargetable debugger, noweb (literate programming) dblp
Nagarajan Ranganathan	Professor U of South Florida vcapp.csee.usf.edu/~ranganat	JPEG 128x147 128x147	VLSI Algorithms and architectures, application specific VLSI system design, VLSI design automation, data compression, VLSI for image/video/signal processing, computer architecture and parallel computing dblp
Parthasarathy Ranganathan	Hewlett Packard WRL research.compaq.com/wrl/people/parthas/bio.html	GIF 68x85 68x85	computer architecture, parallel computing, performance evaluation, low-power system design dblp
Srikantam Sai Surya Prakasa Rao	Professor Indian Institute of Technology, Bombay, India cse.iitb.ac.in/~ssspr/personal.html	JPEG 93x101 93x101	VLSI Design, computer architecture, reconfigurable computing, microprocessor design and interfaces dblp
Justin R. Rattner	director Microprocessor Research, Intel intel.com/pressroom/kits/bios/jrattner.htm	GIF 262x357 262x357	ASCII Red, advanced circuits, microarchitecture, architecture dblp
Bob Ramakrishna Rau	(deceased) Hewlett-Packard Labs trimaran.org/car_group/bob_rau.html Eckert-Mauchly (2002) award	GIF 100x121 100x121	VLIW, EPIC, Elcor, Trimaran, PICO, rotating register files, Cydra 5 dblp
Lawrence Rauchwerger	Professor Texas A&M U, CS cs.tamu.edu/faculty/rwerger	JPEG 160x203 160x203	speculative parallelization, Polaris dblp
Daniel A. Reed	Professor U of Illinois at Urbana-Champaign, CS www-pablo.cs.uiuc.edu/People/Reed/DanReed.htm	JPEG 284x346 284x346	performance analysis techniques and resource management for parallel systems dblp
John Regehr	Professor U of Utah, CS cs.utah.edu/~regehr	JPEG 118x149 118x149	embedded systems dblp
Jakob Rehof	Microsoft Research research.microsoft.com/~rehof	JPEG 157x209 157x209	type systems, type inference, model checking and type systems for concurrent programs, static program analysis, program logics, complexity and scalability of program analyses dblp
Steven K. Reinhardt	Professor U of Michigan eecs.umich.edu/~stever	JPEG 132x185 132x185	computer architecture, parallel and distributed systems, operating systems, computer system simulation dblp
Glenn Reinman	Professor UC Los Angeles cs.ucla.edu/~reinman	JPEG 111x136 111x136	computer architecture, ILP, speculative execution, branch prediction and fetch architectures, cache design and prefetching, CACTI, scalable architectures dblp
Didier Rémy	Researcher INRIA Rocquencourt, France pauillac.inria.fr/~remy/	JPEG 107x142 107x142	type systems and type inference, object oriented languages, concurrent and distributed languages, semantics of programming languages, Ocaml, Join dblp
Jose Renau	Professor UC Santa Cruz coe.ucsc.edu/~renau	JPEG 94x128 94x128	energy/performance trade-offs, thread level speculation, simulation tools, FPGAs, complexity dblp
John H. Reppy	Professor U of Chicago people.cs.uchicago.edu/~jhr	?	design and implementation of advanced programming languages, Moby, SML/NJ dblp
Thomas W. Reps	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~reps/reps.html	JPEG 234x300 234x300	program slicing, shape analysis, model checking dblp
John C. Reynolds	Professor Carnegie Mellon U, CS cs.cmu.edu/~jcr	JPEG 86x110 86x110	design of programming languages, semantics of programming languages, methods for proving that programs meet specifications dblp
Laura Ricci	Professor U of Pisa, Italy di.unipi.it/~ricci	?	compilation and modelling of HPC, parallelization of irregular applications, static analysis dblp
Martin C. Rinard	Professor MIT cag.lcs.mit.edu/~rinard	GIF 131x182 131x182	commutativity analysis, compilers, multithreaded program analysis dblp
Dennis M. Ritchie	Bell Labs, Lucent cm.bell-labs.com/cm/cs/who/dmr Turing (1983) award	GIF 84x105 84x105	C, Unix dblp
Scott Rixner	Professor Rice U, CS cs.rice.edu/~rixner	JPEG 270x388 270x388	microprocessor architecture, media and network processing, VLSI and computer architectures, memory system architecture dblp
Davide Rizzo	ST Microelectronics	?	architectural support for multimedia dblp
Anne Rogers	Prfessor U of Chicago, CS people.cs.uchicago.edu/~amr	JPEG 178x214 178x214	compilers, Olden, parallel programming dblp
Ronny Ronen	Israel Microarchitecture Lab Director Intel intel.com/research/mrl/people/ronen_r.htm	JPEG 85x109 85x109	microprocessor architecture and microarchitecture, compilers dblp
Jonathan Rose	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~jayar	JPEG 130x173 130x173	FPGAs architecture, CAD, Field-Programmable Systems, graphics and vision applications on FPGAs dblp
Mendel Rosenblum	Professor Stanford U/Vmware simos.stanford.edu/~mendel	GIF 106x127 106x127	SimOS, FLASH, Hive, Disco, log-structured filesystem dblp
Guido van Rossum	Elemental Security python.org/~guido	JPEG 147x180 147x180	Python, Amoeba, hypermedia dblp
Grigore Rosu	Professor U of Illinois at Urbana-Champaign, CS gureni.cs.uiuc.edu/~grosu	JPEG 131x198 131x198	design/semantics/implementation of programming and specification languages, certification/monitoring/synthesis/modularization, automated reasoning, algorithms, category theory dblp
Eric Rotenberg	Professor North Carolina State U, ECE tinker.ncsu.edu/ericro	JPEG 123x169 123x169	Trace cache, Slipstream processors dblp
Amir Roth	Professor U of Pennsylvania cis.upenn.edu/~amir	JPEG 211x251 211x251	multithreaded processors, prediction dblp
Jerry Roth	Professor Gonzaga U cps.gonzaga.edu/~roth	GIF 106x136 106x136	optimizing compiler technology for scalar and parallel architectures dblp
Kaushik Roy	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~kaushik	JPEG 132x171 132x171	low power VLSI dblp
Elizabeth M. Rudnick	Professor U of Illinois Urbana-Champaign, ECE crhc.uiuc.edu/~liz	JPEG 69x85 69x85	design verification, test generation, fault simulation, design for testability, fault diagnosis, VLSI system design, electronic design automation dblp
Larry Rudolph	professor MIT csg.lcs.mit.edu/~rudolph	JPEG 290x343 290x343	starT, parallel computation, Oxygen dblp
Erik Ruf	Microsoft Research research.microsoft.com/~ruf	JPEG 75x75 75x75	design and implementation of programming languages, Bartok, AST toolkit dblp
Radu Rugina	Professor Cornell U, CS cs.cornell.edu/People/rugina	JPEG 114x166 114x166	multithreaded prog. pointer analysis, automatic paralellization dblp
Rob A. Rutenbar	Professor Carnegie Mellon U, ECE ece.cmu.edu/~rutenbar	GIF 56x83 56x83	custom analog circuit CAD, high-performance digital ICs and CAD dblp
Oliver Rüthing	post doc (old) U of Dortmund, Germany ls5-www.cs.uni-dortmund.de/~ruething	?	static analysis, lazy code motion dblp
Barbara G. Ryder	Professor Rutgers U, CS cs.rutgers.edu/~ryder	GIF 138x164 138x164	compile-time program analyses, tools for program understanding/testing/maintenance, optimization of object-oriented programs, static and dynamic program analyses in server systems dblp
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Shmuel Sagiv	Professor Tel Aviv U, Israel math.tau.ac.il/~msagiv	JPEG 282x355 282x355	programming languages, compilers, abstract interpretation, profiling, pointer analysis, interprocedural dataflow analysis, program slicing, porting source code, language-based programming environments dblp
Sartaj K. Sahni	Professor U of Florida cise.ufl.edu/~sahni	JPEG 255x337 255x337	data structures and algorithms, scheduling, optimization, VLSI CAD, computational geometry, image processing, medical applications dblp
Pascal Sainrat	U Paul Sabatier, Toulouse, France irit.fr/recherches/ARCHI/MARCH/SAINRAT/ANGLAIS/sainrat.frame.shtm	GIF 76x86 76x86	interconnection networks, superscalar architectures dblp
Suleyman Sair	Professor North Carolina State U ECE cesr.ncsu.edu/ssair	JPEG 339x451 339x451	computer architecture, phase-based program analysis and optimizations, adaptive scheduling for VLIW, memory hierarchy design and prefetching dblp
Karem A. Sakallah	Professor U of Michigan eecs.umich.edu/~karem	JPEG 135x191 135x191	VLSI, CAD, timing verification, optimal clocking dblp
Rizos Sakellariou	Lecturer U of Manchester, UK cs.man.ac.uk/~rizos	JPEG 60x64 60x64	parallel and distributed systems, optimising and parallelising compilers, performance modelling, software support for metacomputing and the Grid, Internet computing dblp
Mariagiovanna Sami	Professor Politecnico di Milano, Italy elet.polimi.it/internet/personai.asp?ID=sami	JPEG 65x68 65x68	digital architecture design, defect and fault-tolerance of digital architectures, parallel architectures, low-power design, high-level synthesis dblp
Eduardo Sanchez	Logic Systems Laboratory, Lausanne, Switzerland lslwww.epfl.ch/pages/staff/sanchez	JPEG 145x193 145x193	high complexity programmable circuits, cellular networks dblp
Alberto L. Sangiovanni-Vincentelli	Professor UC Berkeley, ECE www-cad.eecs.berkeley.edu/~alberto	GIF 147x194 147x194	design technology, computer-aided analysis and design, embedded system design dblp
Vivek Sarkar	IBM T. J. Watson research.ibm.com/people/v/vsarkar	JPEG 87x126 87x126	Java, Jalapeno, array SSA, compilers dblp
Majid Sarrafzadeh	Professor Northwestern U ECE ece.northwestern.edu/~majid/	JPEG 141x195 141x195	VLSI CAD, physical design, low-power design, reconfigurable computing and FPGAs, embedded systems, design and analysis of algorithms, computational complexity dblp
Toshinori Sato	Professor Kyushu Institute of Technology, Iizuka, Japan mickey.ai.kyutech.ac.jp/~tsato	GIF 163x165 163x165	microprocessor architecture and design dblp
Ashley Saulsbury	Sun	?	Simple COMA, memory hierarchies dblp
Yiannakis Sazeides	Professor U of Cyprus, Greece cs.ucy.ac.cy/~yanos	?	computer architecture, high performance microprocessors, ILP, predictability, novel execution paradigms, simultaneous multithreading dblp
Klaus E. Schauser	Professor UC Santa Barbara, CS cs.ucsb.edu/~schauser	GIF 95x132 95x132	parallel computing, Java-based global computing, SCI-based cluster computing, compilers, computer architecture dblp
Isaac D. Scherson	Professor UC Irvine ics.uci.edu/~isaac	JPEG 175x256 175x256	operating systems for parallel computers, interconnection networks, performance evaluation, parallel algorithms, simulation models dblp
Michael S. Schlansker	Hewlett-Packard trimaran.org/car_group/mike_schlansker.html	GIF 92x116 92x116	EPIC, embedded systems dblp
Herman Schmit	Professor Carnegie Mellon U, ECE ece.cmu.edu/~herman (old)	GIF 68x88 68x88	reconfigurable hardware, PipeRench dblp
Yannis Schoinas	Intel cs.wisc.edu/~schoinas/schoinas.html (old)	JPEG 177x196 177x196	parallel systems, system area networks, operating systems, computer systems architecture dblp
Robert Schreiber	Project scientist Hewlett-Packard Labs trimaran.org/car_group/rob_schreiber.html	GIF 109x136 109x136	Trimaran, Elcor, matrix algorithms, MATLAB, HPF dblp
Michael Schulte	Professor Lehigh U eecs.lehigh.edu/~mschulte	JPEG 53x66 53x66	hardware and software for numerical computations, architectures and compilers for DSP, application-specific processor design, architectures and compilers for interval arithmetic dblp
Martin Schulz	Postdoc Cornell U, ECE csl.cornell.edu/~schulz	JPEG 128x160 128x160	parallel languages and tools, SCI-based multiprocessor systems and clusters, hybrid software and hardware DSM systems, shared memory programming models, monitoring and tool support for shared memory programming, distributed and parallel I/O for clusters dblp
Assaf Schuster	Professor Israel Institute of Technology (Technion) cs.technion.ac.il/~assaf	JPEG 60x82 60x82	parallel and distributed computing, peer-to-peer computing, large-scale data mining, scalable model checking, high-performance computer architecture, shared memory consistency models, Java memory model, distributed shared memory, fault tolerance, non-stop systems dblp
Michael I. Schwartzbach	Professor U of Aarhus, Denmark brics.dk/~mis	GIF 142x179 142x179	programming language design/implementation/analysis, monadic second-order logic, web technology dblp
Dana S. Scott	Professor (emeritus) Carnegie Mellon U, CS cs.cmu.edu/~scott Turing (1976) award	GIF 192x256 192x256	logic, type theory, philosophy, non-deterministic finite-state machines, realizability, domain theory dblp
Michael L. Scott	Professor U of Rochester, CS cs.rochester.edu/u/scott	JPEG 138x185 138x185	parallel and distributed systems software, multiprocessor synchronization and memory coherence, operating systems, program development tools, compiler technology, programming language design dblp
Steve Scott	Cray Inc Maurice Wilkes (2005) award	JPEG 75x95 75x95	interconnection networks, synchronization, multiprocessor cache coherence dblp
Carl-Johan H. Seger	Intel Strategic CAD Labs intel.com/research/scl/people/seger_c.htm	JPEG 84x112 84x112	hardware verification, asynchronous circuits dblp
Peter-Michael Seidel	Professor Southern Methodist U seas.smu.edu/~seidel	GIF 190x258 190x258	computer arithmetic dblp
Luc Séméria	R&D Engineer Synopsis Inc. chronos.stanford.edu/users/lucs	JPEG 246x308 246x308	hardware synthesis from C/C++ dblp
Ravi Sethi	President Avaya Labs cm.bell-labs.com/who/ravi (old)	JPEG 66x85 66x85	compilers dblp
Julian Seward	ukuug.org/bios+profiles/JSeward.shtml	?	Glascow Haskell Compiler, valgrind, bzip dblp
André Seznec	Research director IRISA/INRIA, France irisa.fr/caps/people/seznec/index_en.htm	JPEG 109x132 109x132	cache architecture, processor organisation, sequencing and branch prediction, simultaneous multithreading, SALTO, Calvin2+DICE, truly random number generation dblp
Edwin Sha	Professor U of Texas at Dallas utdallas.edu/~edsha	JPEG 103x123 103x123	parallel processing, parallel architectures, high-level synthesis in VLSI, fault-tolerant computing, CAD for application-specific systems, VLSI architectures, software tools for parallel and distributed systems dblp
Hazim Shafi	IBM Research www-ece.rice.edu/~shafi	GIF 84x109 84x109	computer architecture, parallel and distributed computation dblp
Naresh R. Shanbhag	Professor U of Illinois at Urbana-Champaign, ECE cims.csl.uiuc.edu/~shanbhag/myhome	JPEG 171x237 171x237	communication systems and IC design, noise-tolerant VLSI, bounds on energy and throughput efficiency of integrated microsystems dblp
Mark Shand	Hewlett-Packard System Research Center research.compaq.com/SRC/personal/shand/home.html	GIF 113x148 113x148	reconfigurable computing, PCI Pamette dblp
Natarajan Shankar	SRI International csl.sri.com/users/shankar/shankar.html	JPEG 138x176 138x176	linear logic and proof theory, formal methods program, PVS dblp
Priti Shankar	Professor Indian Institute of Science, Bangalore, India drona.csa.iisc.ernet.in/~priti	?	compiler tools, coding theory, automata theory and formal languages dblp
Claude E. Shannon	(deceased) Bell Labs, Lucent/MIT web.mit.edu/newsoffice/tt/2001/feb28/obitshannon.html National Medal of Science	JPEG 159x215 159x215	information theory, coding theory, cryptography dblp
John Paul Shen	Director, Microarchitecture Research Intel intel.com/pressroom/kits/bios/jshen.htm	GIF 73x91 73x91	microarchitecture dblp
Kenneth L. Shepard	Professor Columbia U, CS cisl.columbia.edu/faculty/shepard	JPEG 448x569 448x569	design tools for advanced CMOS, SOI circuits, on-chip test and measurement circuitry, low-power design for DSP, CMOS gene chips dblp
Timothy Sherwood	Professor UC Santa Barbara CS cs.ucsb.edu/~sherwood	JPEG 78x112 78x112	computer architecture, embedded systems, program phase behavior, SimPoint dblp
Olin Shivers	Professor Georgia Tech U, CS cc.gatech.edu/~shivers	GIF 206x279 206x279	advanced programming languages, systems, personal user interfaces, Scheme dblp
Sandeep K. Shukla	Professor Virginia Tech, ECE filebox.vt.edu/users/shukla	JPEG 106x110 106x110	formal methods, system level power management, system level design and verification, ad-hoc networks dblp
Howard Jay Siegel	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~hj	JPEG 64x79 64x79	parallel processing, heterogeneous computing, computer architecture, interconnection networks, parallel algorithms dblp
Daniel P. Siewiorek	Director of Human Computer-Interaction Institute Carnegie Mellon U cs.cmu.edu/~dps Eckert-Mauchly (1988) award	GIF 111x153 111x153	wearable computers, fault tolerance, CM* dblp
Gabriel M. Silberman	IBM Software Solutions Divisions, Toronto, Canada cas.ibm.com/director	JPEG 79x112 79x112	computer architecture, compilers, digital circuit testing dblp
Jurij Silc	Researcher Jozef Stefan Institute, Ljubljana, Slovenia anica.ijs.si/silc	JPEG 137x180 137x180	processor architecture, multithreaded computing, high-level synthesis, parallel processing, evolution algorithms dblp
Elizabeth A. Simon	Professor U of San Diego CS sandiego.edu/~bsimon	JPEG 94x106 94x106	compilers, computer architecture, performance programming, scientific computing, EPIC compilation dblp
Tajana Simunic	Hewlett-Packard Labs akebono.stanford.edu/users/tajana/	JPEG 69x88 69x88	system-level hardware and software design, wireless, embedded and low-power systems dblp
Jaswinder Pal Singh	Professor Princeton U, CS cs.princeton.edu/~jps	GIF 67x87 67x87	parallel architectures dblp
Montek Singh	Professor U of North Carolina CS cs.unc.edu/~montek	JPEG 200x214 200x214	high-performance and low-power digital design, VLSI CAD, asynchronous circuits dblp
Satnam Singh	Microsoft Research xilinx.com/labs/satnam (old)	GIF 168x204 168x204	hardware description languages, formal verification for core verification, reconfigurable computing, layout analysis dblp
Henk J. Sips	Professor Delft U, Netherlands pds.twi.tudelft.nl/~henk	JPEG 140x167 140x167	parallel algorithms, parallel computer architecture, parallel programming languages dblp
Mukund Sivaraman	R&D engineer Hewlett-Packard Labs, Compiler and Architecture Group hpl.hp.com/research/itc/car/Templates/mukund-sivaraman-page.html	JPEG 281x324 281x324	timing and functional verification for ASIC, PICO dblp
Anand Sivasubramaniam	Professor Penn State U cse.psu.edu/~anand	GIF 119x156 119x156	computer architecture, operating systems, parallel computing, simulation and evaluation of dblp
Kevin Skadron	Professor U of Virginia, CS cs.virginia.edu/~skadron	JPEG 181x248 181x248	HydraScalar, multipath execution dblp
Alexander Skavantzos	Professor Louisiana State U ece.lsu.edu/alex	JPEG 154x193 154x193	computer arithmetic, computer architecture, ASIC design, VLSI signal processing, parallel processing dblp
Jonas Skeppstedt	Professor Lunds U, Sweden cs.lth.se/~js	JPEG 233x306 233x306	compiler controlled data prefetching dblp
Konrad Slind	Professor U of Utah, CS cs.utah.edu/~slind	JPEG 128x171 128x171	higher order logic, formal verification dblp
Yannis Smaragdakis	Professor Georgia Tech U, CS cc.gatech.edu/~yannis	JPEG 97x125 97x125	object-oriented language design, tools to facilitate program construction, memory management dblp
Alan J. Smith	Professor UC Berkeley, CS cs.berkeley.edu/People/Faculty/Homepages/smith.html	GIF 76x108 76x108	caches, power management dblp
Burton J. Smith	Chief scientist Cray Inc Eckert-Mauchly (1991) award	GIF 165x241 165x241	high-performance computer architecture, parallel programming languages, MTA dblp
James E. Smith	Professor U of Wisconsin-Madison, ECE engr.wisc.edu/ece/faculty/smith_james.html Eckert-Mauchly (1999) award	GIF 106x132 106x132	Trace cache, Trace processor, Multiscalar dblp
Michael D. Smith	Professor Harvard U eecs.harvard.edu/~smith	GIF 140x148 140x148	Machsuif, compiler back-end dblp
Mark Smotherman	Professor Clemson U cs.clemson.edu/~mark	JPEG 64x76 64x76	reliability, performance modeling, computer architecture dblp
Greg Snider	Hewlett-Packard Labs trimaran.org/car_group/greg_snider.html (old)	GIF 98x124 98x124	Elcor, compilation for reconfigurable hardware, PICO dblp
Marc Snir	Professor U of Illinois at Urbana-Champaign, CS www-sal.cs.uiuc.edu/~snir	JPEG 113x150 113x150	IBM Blue Gene, NYU Ultracomputer, MPI, IBM SP scalable parallel system, parallel algorithms, parallel architectures, interconnection networks, parallel programming environments dblp
Avinash Sodani	Intel, Hillsboro cs.wisc.edu/~sodani/sodani.html (old)	GIF 58x69 58x69	dynamic instruction reuse dblp
Mary Lou Soffa	Professor U of Virginia, CS cs.virginia.edu/~soffa	JPEG 96x124 96x124	continuous and adaptive compilation, path and resource sensitive optimizations, experimental evaluation of optimizations, debugging optimized code, demand driven data flow, GUI testing dblp
Gurindar S. Sohi	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~sohi Maurice Wilkes (1999) award	GIF 134x203 134x203	Multiscalar, speculative execution dblp
Yan Solihin	Professor North Carolina State U cesr.ncsu.edu/solihin	JPEG 157x207 157x207	memory hierarchy organization, asymmetric architecture, customizable threads, processor-memory integration, self-optimizing systems dblp
Arun K. Somani	Professor Iowa State U, EE vulcan.ee.iastate.edu/~arun	JPEG 100x127 100x127	fault tolerant computing, computer interconnection networks, optical networking, computer architecture, parallel computer systems dblp
Fabio Somenzi	Professor U of Colorado at Boulder, ECE vlsi.colorado.edu/~fabio	GIF 128x163 128x163	formal verification, CUDD, VIS, CAD, logic minimization dblp
Daniel J. Sorin	Professor Duke U, EE ee.duke.edu/~sorin	JPEG 97x137 97x137	SMP, high availability servers, memory system design, verification of memory consistency, performance analysis dblp
Christos P. Sotiriou	Professor ICS-FORTH, Heraklion, Crete, Greece ics.forth.gr/~sotiriou	?	asynchronous circuit design and testing, industrial EDA tools for asynchronous design dblp
Jens Sparsø	Professor Technical U of Denmark imm.dtu.dk/~jsp	JPEG 314x422 314x422	architecture and design of VLSI systems, asynchronous logic dblp
Evan Speight	Professor Cornell U, ECE csl.cornell.edu/~espeight	JPEG 115x128 115x128	distributed computing, parallel processing, computer architecture, location-independent data access, operating systems dblp
Ellen Spertus	Professor Mills College mills.edu/ACAD_INFO/mcs_spertus.html	GIF 133x145 133x145	information retrieval, Internet, social issues, computer architecture, compilers dblp
Amitabh Srivastava	Vice President Microsoft research.microsoft.com/users/amitabhs	JPEG 276x337 276x337	ATOM, programmer productivity, software engineering dblp
Richard M. Stallman	President Free Software Foundation stallman.org	JPEG 304x372 304x372	Emacs, gcc, bison dblp
Mircea Stan	Professor U of Virginia, EE ee.virginia.edu/~mrs8n	JPEG 194x291 194x291	low-power encoding methods and circuits, CAD for high-level power estimation, circuit design for novel low-power devices, low-power system integration dblp
Bjarne Steensgaard	Researcher Microsoft Research research.microsoft.com/~rusa	JPEG 75x75 75x75	alias analysis, VDG, Java, C dblp
Darko Stefanovic	Professor U of New Mexico CS cs.unm.edu/~darko	?	dynamic cooperative performance optimization for Java, dynamic binary translation, computing with biochemical molecules dblp
J. Gregory Steffan	Professor U of Toronto, EE, Canada eecg.toronto.edu/~steffan	GIF 192x256 192x256	thread-level data speculation dblp
Bernhard Steffen	Professor U of Dortmund, Germany ls5-www.cs.uni-dortmund.de/staff/steffen.en.html	GIF 135x182 135x182	static analysis, lazy code motion, formal verification dblp
Per Stenström	Professor Chalmers U, Goteborg, Sweden ce.chalmers.se/~pers	GIF 69x83 69x83	high-performance computers, multiprocessors for multimedia/database/numeric applications dblp
Thomas L. Sterling	Professor Caltech U cacr.caltech.edu/~tron	JPEG 99x108 99x108	Beowulf, Hybrid Technology Multithreaded Architecture (HTMT), parallel computer architecture, system software, evaluation dblp
James E. Stine	Professor Illinois Institute of Technology, ECE ece.iit.edu/~jstine	JPEG 94x131 94x131	computer arithmetic, computer architecture, VLSI, CAD techniques, reliable computing, compilers, digital circuit design, FPGA and DSP architectures dblp
Paul Stodghill	Research Associate Cornell U, CS cs.cornell.edu/stodghil	JPEG 139x199 139x199	sparse compilation, sparse computations, fault-tolerance and dynamic resource management for scientific computations, extensible and open compiler systems, programming systems for HPC dblp
Mark G. Stoodley	U of Toronto, Canada eecg.toronto.edu/~stoodla	JPEG 164x208 164x208	low-level compiler optimizations and related architectural features, vector microprocessors dblp
Quentin F. Stout	Professor U of Michigan eecs.umich.edu/~qstout	GIF 66x66 66x66	parallel and scientific computing, adaptive sampling designs, algorithms and data structures, operator theory and analysis dblp
Andrzej J. Strojwas	Professor Carnegie Mellon U, ECE ece.cmu.edu/people/show.php?type=faculty&id=171	GIF 83x94 83x94	design and manufacturing of ULSIC dblp
Bjarne Stroustrup	AT&T Research/Texas A&M U research.att.com/~bs/homepage.html ACM Grace Murray Hopper award (1983) award	JPEG 202x250 202x250	C++ dblp
Volker Strumpen	Research scientist MIT cag.lcs.mit.edu/~strumpen	?	Porch: portable checkpoint compiler, Cilk, distributed operating systems, RAW operating system dblp
Michael Stumm	Professor U of Toronto, Canada eecg.utoronto.ca/~stumm	JPEG 150x206 150x206	operating systems for distributed and parallel systems, multiprocessor architectures, DSM, parallel file systems, parallel compilers, Hector Multiprocessor, Hurricane OS, NUMAchine multiprocessor, Tornado OS dblp
Zhendong Su	Professor UC Davis, CS cs.ucdavis.edu/~su	JPEG 94x132 94x132	static analyses for error detection dblp
Bronis R. de Supinski	Lawrence Livermore National Lab llnl.gov/CASC/people/de_supinski	JPEG 155x213 155x213	cache coherence and distributed shared memory, consistency semantics, networks of workstations, distributed object computing, parallel and distributed simulation dblp
Ivan E. Sutherland	Sun sun.com/960710/feature3/ivan-profile.html Turing (1988) award, von Neumann medal, computer graphics award	JPEG 157x220 157x220	asynchronous logic, micropipelines, Counterflow dblp
Bertil P. Svensson	Professor Chalmers U, Goteborg, Sweden ce.chalmers.se/People/svensson.html	JPEG 81x120 81x120	parallel processing for embedded systems, distributed massively parallel architectures, neurocomputers, real-time systems dblp
Philip H. Sweany	Texas Instruments	GIF 86x101 86x101	compilation for VLIW dblp
Peter F. Sweeney	IBM Research T. J. Watson research.ibm.com/people/p/pfs/	JPEG 126x179 126x179	analysis and optimization of object-oriented languages, software distribution dblp
Dennis Sylvester	Professor U of Michigan eecs.umich.edu/~dennis	JPEG 720x878 720x878	modeling/characterization/analysis of deep submicron device technology dblp
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Mehdi Baradaran Tahoori	Professor Northeastern U ece.neu.edu/faculty/mtahoori	JPEG 169x223 169x223	FPGA Testing, VLSI Test Automation, reliability and fault tolerance, test, defect and fault tolerance for molecular and nano-technology, noise issues in deep sub-micron VLSI, CAD, reconfigurable computing dblp
Deependra Talla	System Architect Texas Instruments ece.villanova.edu/~deepu	JPEG 85x102 85x102	computer architecture, multimedia and DSP, workload characterization, ASIC and FPGA design dblp
Madhusudhan Talluri	Sunsoft, Sun cs.wisc.edu/~talluri/talluri.html (old)	GIF 77x91 77x91	virtual memory dblp
Andrew S. Tanenbaum	Professor Vrije U., Amsterdam, Netherlands cs.vu.nl/~ast/	JPEG 155x206 155x206	distributed systems, compilers, many textbooks dblp
Zhimin Tang	Professor Institute of Computing Technology, Chinese Academy of Sciences ict.ac.cn/chpc/tang	JPEG 87x113 87x113	ASIC design, parallel processing, dblp
Olivier Tardieu	Postdoc Columbia U CS www1.cs.columbia.edu/~tardieu	JPEG 69x82 69x82	alias analysis, embedded systems dblp
Robert Endre Tarjan	Professor Princeton U, CS cs.princeton.edu/~ret Turing (1986) award	GIF 188x272 188x272	graph algorithms dblp
Valerie E. Taylor	Professor Texas A&M U, CS cs.tamu.edu/people/faculty/taylor	JPEG 118x140 118x140	high performance computing, performance analysis and modeling of parallel and distributed applications dblp
Jürgen Teich	Professor U Erlangen-Nuremberg, Germany www12.informatik.uni-erlangen.de/people/teich/index.php	JPEG 1439x1949 1439x1949	embedded systems, scheduling theory and optimization, massively parallel VLSI architectures dblp
Tim Teitelbaum	Professor Cornell U cs.cornell.edu/Info/People/tt/Tim_Teitelbaum.html	GIF 178x228 178x228	incremental computation, transformational programming, programming environments, language-based editors, compilers, attribute grammars, Ada, synthesizer dblp
Olivier Temam	Professor U Paris Sud, France lri.fr/~temam	JPEG 352x423 352x423	microarchitecture, memory locality dblp
Dan Teodosiu	Researcher Microsoft Research	GIF 75x90 75x90	multiprocessors, Scheme, compression dblp
Russell Tessier	Professor U Massachusetts Amherst ecs.umass.edu/ece/tessier	JPEG 150x193 150x193	hardware verification, reconfigurable hardware, CAD and logic synthesis dblp
Charles P. Thacker	Microsoft Research Silicon Valley nae.edu/NAE/awardscom.nsf/weblinks/LRAO-5X4TYX?OpenDocument	JPEG 373x507 373x507	Firefly, Xerox Alto, Tablet PC, Ethernet, AUTONET dblp
Chandramohan A. Thekkath	Microsoft Research research.microsoft.com/~thekkath	JPEG 123x154 123x154	operating systems, distributed systems, networks, interaction architecture/OS dblp
Kevin B. Theobald	Professor U of Delaware capsl.udel.edu/~theobald	JPEG 54x69 54x69	multithreaded architectures, branch prediction, EARTH dblp
Michael Theobald	Postdoc Carnegie Mellon U CS www-2.cs.cmu.edu/~theobald	JPEG 165x214 165x214	asynchronous circuits, formal verification, CAD, logic and high-level synthesis, BDD and SAT Techniques, embedded and hybrid systems dblp
Lothar Thiele	Professor ETH Zurich, Switzerland tik.ee.ethz.ch/~thiele	GIF 111x147 111x147	models/methods/software tools for embedded systems design, array processors, parallel algorithms for signal and image processing, combinatorial optimization, cryptography dblp
Donald E. Thomas	Professor Carnegie Mellon U, ECE ece.cmu.edu/~thomas	GIF 65x88 65x88	hardware/software co-design, Verilog dblp
Carol L. Thompson	Hewlett-Packard	?	compilers for Itanium dblp
Ken Thompson	Bell Labs, Lucent cm.bell-labs.com/cm/cs/who/ken (old) Turing (1983) award	JPEG 98x119 98x119	Unix, Plan 9 dblp
Mithuna S. Thottethodi	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~mithuna	JPEG 147x170 147x170	microarchitecture, communication in distributed microarchitectures, systems architecture, interconnection networks dblp
Michael D. Tiemann	Vice President RedHat Inc. redhat.com/about/corporate/team/tiemann.html	GIF 141x181 141x181	g++, Cygnus dblp
Frank Tip	IBM T.J. Watson research.ibm.com/people/t/tip	JPEG 122x169 122x169	whole-program optimization of object-oriented applications, program analyis/slicing/understanding/refactoring, compiler optimization dblp
Francisco Tirado	Professor U Complutense de Madrid, Spain dacya.ucm.es/paco	JPEG 149x188 149x188	parallel processing for scientific computing, scalability of parallel systems, parallel architectures, processor microarchitecture dblp
Robert Tomasulo	IBM ? Eckert-Mauchly (1997) award	?	Tomasulo's algorithm (out-of-order execution)
Hiroyuki Tomiyama	Professor Nagoya U, Japan ertl.jp/~tomiyama	GIF 79x111 79x111	system-level design methodologies for system-on-chip, high-level synthesis, compilers for low-power embedded systems, analysis and optimization of real-time software dblp
Karen A. Tomko	Professor U of Cincinatti ece.uc.edu/~ktomko	GIF 172x210 172x210	reconfigurable computing, high performance computing, scientific application performance, graph partitioning, compiler assisted optimization dblp
Linda Torczon	Research scientist Rice U, CS cs.rice.edu/~linda	GIF 121x153 121x153	code generation, interprocedural dataflow analysis, ParaScope dblp
Hwa C. Torng	Professor (emeritus) Cornell U, ECE ee.cornell.edu/people/faculty/torng/htorng.shtml	GIF 67x74 67x74	advanced RISC and superscalar architecture, design of intelligent and broadband telecommunication networks, task scheduling in multi-processors dblp
Josep Torrellas	Professor U of Illinois Urbana-Champaign, CS iacoma.cs.uiuc.edu/~torrella	GIF 238x344 238x344	Polaris, I-ACOMA, FlexRAM dblp
Nur A. Touba	Professor U of Texas, Austin, ECE ece.utexas.edu/~touba	GIF 66x81 66x81	CAD, testing, fault tolerant computing dblp
Dan Truong	Hewlett-Packard irisa.fr/caps/people/truong (old)	JPEG 49x55 49x55	software cache optimization, data and instruction layout and prefetching, profile-based optimization dblp
Dean M. Tullsen	Professor UC San Diego www-cse.ucsd.edu/users/tullsen	JPEG 131x171 131x171	SMT, speculation, ILP dblp
Gary Scott Tyson	Professor U of Michigan eecs.umich.edu/~tyson	JPEG 168x232 168x232	computer architecture, compiler optimization dblp
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Gang-Ryung Uh	Professor Boise State U cs.boisestate.edu/~uh	JPEG 184x223 184x223	embedded processors software tools dblp
Augustus K. Uht	Professor U of Rhode-Island ele.uri.edu/~uht	JPEG 173x208 173x208	ILP, timing analysis dblp
Jeffrey D. Ullman	Professor Stanford U www-db.stanford.edu/~ullman	GIF 150x202 150x202	compilers, databases dblp
Stephen H. Unger	Professor Columbia U, CS cs.columbia.edu/~unger	JPEG 139x167 139x167	self-timed systems dblp
Theo Ungerer	Professor U of Augsburg, Germany informatik.uni-augsburg.de/~ungerer/welcome-eng.html	JPEG 162x203 162x203	processor architecture, embedded real-time systems, ubiquitous systems dblp
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Frank Vahid	Professor UC Riverside, CS cs.ucr.edu/~vahid	JPEG 238x314 238x314	embedded systems design dblp
Ramachandran Vaidyanathan	Professor Louisiana State U ECE ece.lsu.edu/vaidy	JPEG 151x209 151x209	parallel algorithms and models, optical interconnects, dynamic reconfiguration, bus-based architectures dblp
Sriram Vajapeyam	consultant cs.wisc.edu/~sriram (old)	?	instruction issue, trace processors, superscalar processor design, run-time program vectorization dblp
Mateo Valero	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/mateo	GIF 80x101 80x101	microarchitecture, compilers dblp
Murali R. Varanasi	Professor U of South Florida csee.usf.edu/faculty/varanasi.htm	GIF 102x135 102x135	coding theory, computer arithmetic, fault tolerant computing, VLSI design dblp
Stamatis Vassiliadis	Professor Technical U of Delft, Netherlands einstein.et.tudelft.nl/~stamatis	JPEG 108x150 108x150	parallel embedded systems, computer architecture, hardware design, custom computing machines, computer arithmetic, low power design, Internet processing dblp
Jack Veenstra	Silicon Graphics cs.rochester.edu/u/veenstra (old)	GIF 72x86 72x86	MINT simulator dblp
Alexander V. Veidenbaum	Professor UC Irvine cecs.uci.edu/~alexv	JPEG 116x139 116x139	computer Architecture, compilers, embedded Systems dblp
Helmut Veith	Professor U of Vienna, Austria dbai.tuwien.ac.at/staff/veith	JPEG 195x247 195x247	formal verification, model checking, temporal logic, security dblp
Andreas G. Veneris	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~veneris/AndreasVeneris.htm	?	CAD tools for synthesis/optimization/testing, algorithms and theory dblp
Mary K. Vernon	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~vernon	JPEG 133x133 133x133	performance modeling dblp
Narayanan Vijaykrishnan	Professor Penn State U cse.psu.edu/~vijay	GIF 94x111 94x111	low power VLSI, Java computing, computer architecture, embedded systems dblp
T. N. Vijaykumar	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~vijay	GIF 100x143 100x143	ILP, Multiscalar, gated-Vdd dblp
Lucian N. Vintan	Professor Lucian Blaga U of Sibiu, Romania webspace.ulbsibiu.ro/lucian.vintan/	JPEG 66x86 66x86	branch prediction, value prediction, prediction techniques for ubiquitous computing dblp
Kees A. Vissers	Trimedia, Netherlands ptolemy.eecs.berkeley.edu/~vissers (old)	JPEG 238x294 238x294	media processors, digital signal processing, hardware-software co-design dblp
Jan Vitek	Professor Purdue U, CS cs.purdue.edu/homes/jv/index.html	JPEG 258x350 258x350	semantics and implementation of programming languages, semantics-based software engineering tools, secure software systems, customizable virtual machines, aliasing and ownership, real-time Java, cluster virtual machines, transactional programming languages dblp
Michael J. Voss	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~voss	JPEG 74x78 74x78	tools and compilers for parallel computing dblp
Zvonko G. Vranesic	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~zvonko	JPEG 191x252 191x252	multiprocessor systems, VLSI systems and local area networks, NUMAchine dblp
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Philip Wadler	Researcher Avaya Labs research.avayalabs.com/user/wadler	JPEG 199x216 199x216	XML, Java, functional languages, Haskell, Erlang, logic and programming dblp
Robert Wagner	Professor Duke U, CS cs.duke.edu/~raw	GIF 157x219 157x219	loop scheduling dblp
Larry Wall	wall.org/~larry	JPEG 172x191 172x191	Perl, patch, rn dblp
Hong Wang	Researcher Santa Clara Intel Microarchitecture Lab intel.com/research/mrl/people/wang_h.htm	JPEG 62x86 62x86	performance modelling, IA-64 dblp
Jun Wang	Professor U of Nebraska, Lincoln cse.unl.edu/~wang	JPEG 350x456 350x456	high performance I/O architectures and storage systems, file systems, peer-to-peer systems, cluster and grid computing, internet server and technology, performance evaluation dblp
Wen-Hann Wang	manager of Emerging Platforms Lab Intel, Hillsboro	?	caches, computer architecture dblp
Nancy J. Warter-Perez	Professor California State U at Los Angeles calstatela.edu/faculty/nwarter/nwareter.htm	GIF 83x103 83x103	computer architecture, high-performance processor design, compiler design, instruction scheduling, EPIC processors dblp
John Wawrzynek	Professor UC Berkeley, CS cs.berkeley.edu/~johnw	GIF 154x180 154x180	BRASS, GARP dblp
Charles C. Weems	Professor U of Massachusetts, Amherst, CS cs.umass.edu/~weems	GIF 108x122 108x122	associative processing and architectures, parallel architectures for image processing, heterogeneous parallel architectures and compilers, integration of compile-time and run-time information dblp
Mark N. Wegman	IBM research.ibm.com/people/w/wegman	JPEG 348x450 348x450	SSA, program optimization, programming languages dblp
William E. Weihl	CTO Akamai akamai.com/en/html/about/management_bw.html	JPEG 126x126 126x126	DCPI, distributed and parallel computing, transaction processing, parallel programming languages, distributed garbage collection, replication, scheduling dblp
Markus Weinhardt	Researcher PACT, Germany markus-weinhardt.de	JPEG 154x161 154x161	reconfigurable hardware compilation dblp
Stephanie Weirich	Professor U of Pennsylvania, CS cis.upenn.edu/~sweirich	JPEG 193x251 193x251	programming languages, type theory, functional programming, logic, language-based security dblp
Daniel Weise	Microsoft Research research.microsoft.com/~daniel	JPEG 107x138 107x138	program slicing, programming languages, VDG dblp
Uri C. Weiser	Director of Streaming Technology, Corporate Technology Group Intel intel.com/pressroom/kits/bios/uweiser.htm	GIF 64x87 64x87	Pentium, MMX dblp
David B. Whalley	Professor Florida State U cs.fsu.edu/~whalley	JPEG 112x158 112x158	optimizing compilers, computer architecture, performance evaluation, real-time systems dblp
Reinhard Wilhelm	Professor U des Saarlandes, Saarbrucken, Germany rw4.cs.uni-sb.de/~wilhelm	JPEG 164x200 164x200	static program analysis, embedded systems, security, animation and visualisation dblp
Maurice V. Wilkes	Advisor on research policy AT&T Research xorl.org/people/mvw Turing (1967) award, Eckert-Mauchly (1980) award	JPEG 107x122 107x122	EDSAC, stored-program computers, microprogramming, caches, distributed memories dblp
Linda M. Wills	Professor Georgia Tech, ECE users.ece.gatech.edu/~linda	JPEG 150x188 150x188	software understanding and retargeting, parallelization of portable multimedia applications, rapid prototyping of reconfigurable embedded software, binary reverse engineering dblp
Scott Wills	Professor Georgia Tech U, ECE users.ece.gatech.edu/~scotty	JPEG 101x131 101x131	focal plane architectures, short wire architectures, VLSI and GSI semiconductor technology, portable multimedia supercomputers, image processing architectures dblp
Steve J. E. Wilton	Professor U of British Columbia, Canada ece.ubc.ca/~stevew	JPEG 215x312 215x312	computer architecture, VLSI design dblp
Jeannette M. Wing	Professor Carnegie Mellon U, CS cs.cmu.edu/~wing	JPEG 129x144 129x144	Software specification and verification, security, concurrent and distributed systems, programming languages, programming methodology dblp
Niklaus Wirth	Professor emeritus ETH Zurich cs.inf.ethz.ch/~wirth Turing (1984) award	JPEG 103x127 103x127	Pascal, Modula-2, Oberon, CAD Tools for Hardware Design (Lola) dblp
Michael J. Wirthlin	Professor Brigham Young U, EE ee.byu.edu/faculty/wirthlin	GIF 133x180 133x180	reconfigurable hardware, JHDL dblp
Emmett Witchel	Professor U of Texas Austin CS cs.utexas.edu/users/witche	JPEG 90x111 90x111	network processors, Mondriaan memory protection, machine learning for scheduling dblp
Mario Wolczko	Senior staff engineer Sun Research research.sun.com/people/mario	JPEG 83x101 83x101	architectural support for object-oriented languages, Mushroom dblp
Tilman Wolf	Professor U of Massachusetts, Amherst ecs.umass.edu/ece/wolf	JPEG 169x220 169x220	network processors, programmable routers dblp
Wayne Wolf	Professor Princeton U, EE ee.princeton.edu/~wolf	GIF 83x108 83x108	embedded computing systems, video architectures, multimedia information systems dblp
Andrew Wolfe	Senior Vice President and CTO SonicBlue sonicblue.com/default.asp?menu=Company&sub_menu=Key_Management&item=Andy_Wolfe	JPEG 68x79 68x79	3D graphic accelerators dblp
Michael R. Wolfe	ST Microelectronics	JPEG 372x484 372x484	parallelizing compilers, vectorization dblp
Martin D. F. Wong	Professor U of Illinois at Urbana-Champaign, ECE ece.uiuc.edu/faculty/faculty.asp?mdfwong	JPEG 107x133 107x133	CAD, field-programmable systems, design and analysis of algorithms, combinatorial optimization dblp
David A. Wood	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~david	JPEG 248x298 248x298	computer architecture, parallel computing, memory systems, performance evaluation dblp
Jim Woodcock	Reader Oxford U, UK web.comlab.ox.ac.uk/oucl/work/jim.woodcock	GIF 89x113 89x113	software engineering, formal methods, mechanised proofs, security and safety, Z dblp
Jie Wu	Professor Florida Atlantic U cse.fau.edu/~jie	JPEG 106x145 106x145	wireless networks and mobile computing, parallel and distributed systems, fault tolerant computing, load balancing in multicomputers, software engineering dblp
Youfeng Wu	Intel MRL intel.com/research/mrl/people/wu_y.htm	JPEG 84x95 84x95	advanced compiler transformations, profile-guided optimizations, instruction-level parallelism, performance analysis with large workloads dblp
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Yuan Xie	Professor Penn State U. cse.psu.edu/~yuanxie	JPEG 157x210 157x210	VLSI design, computer architecture, embedded systems design, electronics design automation (EDA) dblp
Jingling Xue	Professor University of New South Wales, Australia cse.unsw.edu.au/~jxue	JPEG 148x195 148x195	compiler optimisations, instruction-level parallelism, parallelising compilers, memory hierarchies, compilers for embedded systems dblp
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Alex Yakovlev	Professor University of Newcastle, UK staff.ncl.ac.uk/alex.yakovlev	GIF 126x167 126x167	asynchronous vlsi, Petri Nets and concurrency models, Hardware Description Languages, CAD for VLSI, fault tolerance and reliability in VLSI, Petrify dblp
Qing (Ken) Yang	Professor U of Rhode-Island ele.uri.edu/~qyang	GIF 320x384 320x384	distributed web server architectures, disk I/O systems, e-commerce dblp
Yuanyuan Yang	Professor State U of New York at Stony Brook, ECE nrl0.ece.sunysb.edu/~yang	JPEG 365x509 365x509	parallel and distributed computing, high speed networks, optical networks, high performance computer architecture, fault-tolerant computing dblp
Svetlana N. Yanushkevich	Professor U of Calgary, Canada enel.ucalgary.ca/People/yanush	JPEG 182x206 182x206	CAD, multiple-valued logic, decision diagrams, nanoarchitectronics dblp
Hiroto Yasuura	Professor Kyushu U, Japan kasuga.csce.kyushu-u.ac.jp/~yasuura	GIF 58x68 58x68	hardware/software co-design, design methodologies for systems-on-a-chip, embedded system design, information technology for social infrastructure, low power and low energy system design dblp
Katherine Yelick	Professor UC Berkeley, CS cs.berkeley.edu/~yelick	GIF 113x169 113x169	parallel computing, memory hierarchy optimizations, programming languages, compilers dblp
Daniel M. Yellin	director IBM Research Software Technology Department	?	distributed computing, program analysis, algorithms for incremental computation dblp
Donald Yeung	Professor U of Maryland, ECE ece.umd.edu/~yeung	JPEG 100x124 100x124	Vortex, Multigrain systems, MIT Alewife dblp
Pen-Chung Yew	Professor U of Minesotta www-users.cs.umn.edu/~yew	JPEG 57x78 57x78	high-performance microprocessor architectures, parallelizing compilers, parallel machine organizations, performance evaluation, parallel discrete event-driven simulations dblp
Adi Yoaz	Computer Architect Intel Texas Development Center home.austin.rr.com/yoaz	JPEG 144x193 144x193	high performance computing systems, cache architectures, branch prediction, memory disambiguation, data prefetching, speculative execution, ILP dblp
Honesty C. Young	IBM Research, Almaden	?	computer architecture for databases, disk systems dblp
Ki Hwan Yum	Professor U of Texas at San Antonio cs.utsa.edu/~yum	GIF 227x294 227x294	computer architecture, parallel and distributed systems, computer networks, cluster computing, QoS Support in cluster networks and Internet, performance evaluation, fault-tolerant computing, power efficient systems, embedded systems dblp
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F. Kenneth Zadeck	Founder, Chief Technology Officer NaturalBridge	?	program analysis, SSA, optimizing compilers dblp
Mohamed M. Zahran	Professor City U of New York mzahran.com	GIF 155x180 155x180	microarchitecture of multithreaded processors, power-aware architecture, high performance memory hierarchy dblp
Safwat G. Zaky	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~safwat	JPEG 158x205 158x205	computer architecture and hardware, digital circuit design, computer communication, digital switching and LANs, environmental awareness dblp
Andreas Zeller	Professor U des Saarlandes, Germany st.cs.uni-sb.de/~zeller/	JPEG 363x465 363x465	automated debugging, self-healing programs, software evolution, experimental program analysis, exploit generation dblp
Antonia Zhai	Professor U of Minnesota www2.itdean.umn.edu/faculty/detail.jsp?facultyID=503	JPEG 106x123 106x123	compiler optimizations, computer architecture dblp
Lintao Zhang	Microsoft Research research.microsoft.com/users/lintaoz	JPEG 97x108 97x108	formal verification, SAT solvers, Chaff dblp
Wei Zhang	Professor Southern Illinois U, Carbondale ECE howard.engr.siu.edu/~zhang/	JPEG 125x151 125x151	computer architecture, compilers, hardware/software co-design for embedded systems dblp
Xiaodong Zhang	Professor College of William and Mary, CS cs.wm.edu/~zhang	GIF 112x142 112x142	memory performance improvement, memory-centric resource management, cluster computing dblp
Youtao Zhang	Professor U of Texas Dallas utdallas.edu/~yxz028100	JPEG 130x156 130x156	secure systems, program analysis, profiling and code optimization, computer architecture, embedded systems dblp
Zhao Zhang	Professor Iowa State U ECE clue.eng.iastate.edu/~zzhang	GIF 148x214 148x214	high performance computer architecture, parallel and distributed computing, architectural support for security dblp
Xudong Zhao	staff engineer Strategic CAD Labs, Intel	?	formal verification for hardware and arithmetic circuits dblp
Peixin Zhong	Professor Michigan State U ECE egr.msu.edu/~pzhong	JPEG 121x155 121x155	VLSI, computer architecture, adaptable system-on-chip dblp
Dian Zhou	Professor U of Texas at Dallas utdallas.edu/~zhoud	JPEG 149x170 149x170	VLSI, CAD tools, circuits and systems dblp
Hai Zhou	Professor Northwestern U ECE ece.northwestern.edu/~haizhou	JPEG 93x125 93x125	VLSI CAD, algorithm design, formal methods dblp
Huiyang Zhou	Professor U of Central Florida CS cs.ucf.edu/~zhou/	JPEG 115x173 115x173	computer architecture, high-performance/low-power/DSP, back-end compiler design, code optimization, embedded systems dblp
Yuanyuan Zhou	Professor U of Illinois at Urbana-Champaign CS www-faculty.cs.uiuc.edu/~yyzhou	JPEG 289x321 289x321	operating systems, file and storage systems, computer architecture, distributed systems, parallel systems, system support for databases dblp
Jianwen Zhu	Professor U of Toronto, EE, Canada eecg.toronto.edu/~jzhu	JPEG 339x395 339x395	computer aided design for digital IC, synthesis, OpenJ dblp
Sotirios G. Ziavras	Professor New Jersey Institute of Technology megahertz.njit.edu/~ziavras	JPEG 157x222 157x222	computer architecture, parallel processing and supercomputing dblp
Craig B. Zilles	Professor U of Illinois at Urbana-Champaign, CS www-faculty.cs.uiuc.edu/~zilles	JPEG 163x229 163x229	dynamic program slicing, prediction dblp
Hans P. Zima	Professor U of Vienna, Austria par.univie.ac.at/~zima	GIF 107x145 107x145	parallel computation, HPF+, object-based distributed programming for massively parallel arrays of processor-in-memory systems dblp
Wolf Zimmermann	Professor Martin-Luther U Halle-Wittenberg, Germany informatik.uni-halle.de/~zimmer	JPEG 132x173 132x173	reliable compilers, software engineering, programming languages dblp
Benjamin G. Zorn	Microsoft Research research.microsoft.com/~zorn	JPEG 75x75 75x75	hybrid value predictors, garbage collection, programming languages, runtime environments dblp
Konrad Zuse	(deceased) konrad-zuse.de	JPEG 115x134 115x134	first program-controlled digital computer dblp
Willy Zwaenepoel	Professor Rice U, CS cs.rice.edu/~willy	GIF 244x300 244x300	DSM, Munin, Threadmarks, ScalaServer, Puppeteer dblp
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