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ABSTRACTCarnegie Mellon, School of Computer ScienceA Storage Model to Bridge the Processor/Memory Speed Gap Anastassia Ailamaki (joint work with David DeWitt and Mark Hill) Carnegie Mellon University Memory speeds in today’s computers have fundamentally lagged behind processor speeds [7]. Today's memory systems incur access latencies that are up to three orders of magnitude larger than the latency of a single arithmetic operation. To alleviate the processor/memory performance gap, computer designers employ a hierarchy of cache memories (e.g., three levels in the recently announced IBM Power 4 processors), in which each level trades off higher capacity for faster access times. As database applications become increasingly memory-intensive, high performance database systems must maximize cache utilization by keeping data that are likely to be referenced in the cache hierarchy. Ideally, the database application should run under the illusion that the database is cache-resident, i.e., the processor should never be idle due to main memory latency. FULL PAPER: pdf |