CALL FOR PAPERS FOR THE SESSION ON
                      Computing on Bus-Based Architectures

        International Conference on Parallel and Distributed Processing
                     Techniques and Applications (PDPTA'97)
                                  New Horizons

                              June 30-July 2, 1997
                            Las Vegas, Nevada,  USA



SPECIAL SESSION ON COMPUTING ON BUS-BASED ARCHITECTURES:

The special session on Computing on Bus-Based Architectures is planned
to cover different aspects of theory and applications with bus-based
architectures. Bus-based architectures refer to the class of networks
where arrays of processors are enhanced by various bus systems.  The
simple case is a mesh with multiple broadcasting. Adding switches to the
buses, a reconfigurable mesh is obtained where a bus configuration can
be reconfigured dynamically by setting local switches during the
execution of programs.  More recently, several optical buses have been
proposed to connect arrays of processors where messages can be
transmitted concurrently in a pipelined fashion.  Reconfigurable optical
buses have also been proposed as a basic computational model.  The study
of computing on bus-based architectures is a new and fast growing field.
Many technical papers have been published in this area.  Through a
series of elegant results, the usefulness of arrays with various bus
systems has been demonstrated.  The presentations in this special
session will be selected to address both capabilities and limitations of
arrays with various bus systems and their relationships.  The papers in
this special session will describe new research on the various aspects
of parallel computing on bus-based architectures.

Topics of interest include, but not limited to:

        Arrays with multiple broadcasting
        Arrays with a reconfigurable bus system
        Arrays with an optical bus system
	Reconfigurable multibus network
        Algorithm Design (arithmetic/geometric/graph/numerical/randomised)
        Embedding of Fixed Topologies
        Image Processing
        Time Complexity
        Scalability analysis
        Emulation among different models
	Performance evaluation

SUBMISSION OF PAPERS:

To submit an original research paper, send your complete manuscript (not
to exceed 12 single-spaced pages of text using point size 11 type on 8
1/2 X 11 inch or A4 pages) to the Session Chair.  References, figures,
tables, etc.  must be included in the 12 pages.  Electronic submissions
are encouraged and should be sent to pan@hype.cps.udayton.edu.

Electronic submissions must be in the form of a readable postscript file
con- taining the following header information in ASCII form: title,
author name(s), abstract, postal address, e-mail address, and telephone
and fax numbers. The header (in ASCII) should be followed by the
postscript version of the complete manuscript (including title, author's
name, affiliation, and abstract).


EVALUATION PROCESS:

Papers will be evaluated for originality, significance, clarity, and
soundness.  Each paper will be refereed by at least two researchers in
the area.

PUBLICATION:

The conference proceedings will be published by CSREA Press.  Papers
that report significant results will be considered for publication in
relevant journals.

IMPORTANT DATES:

      February 19, 1997 (Wednesday): Draft papers (5-page) due
           April  8, 1997 (Tuesday): Notification of acceptance
              May 19, 1997 (Monday): Camera-Ready papers & Preregistration due


SESSION CHAIR ADDRESS:

Dr. Yi Pan
Computer Science Department
University of Dayton
Dayton, OH 45469-2160, USA
Phone: (513) 229-3807
FAX:   (513) 229-4000
Email: pan@hype.cps.udayton.edu

For information on the last two PDPTA conferences (PDPTA'95 and
PDPTA'96), refer to: http://www.cps.udayton.edu/~pan/pdpta.