15740- Fall 2003 Computer
Architecture
Group Members:
Pratyusa Manadhata, Vyas Sekar
DISCUSSIONS:
Simultaneous
Multithreading
(Slides) (Report: pdf)
(Report: ps)
Vector Processors
(Slides) (Report:
pdf)
PROJECT:
Evaluating Throughput and Fairness of Thread Fetch Policies for SMT
Processors
Abstract:
Simultaneous Multithreading has been
presented as a throughput enhancement paradigm for processor design.
The key to the superior performance of SMT processors is the ability
to exploit both thread-level and instruction-level parallelism, thereby
minimizing the wastage of processor cycles. An important factor that
affects the performance is the choice of threads to select
instructions for dispatch. There have been numerous heuristics aimed
at maximizing the overall throughput of the system. However in a
multi-programming workload, fairness is also important as it affects
the per-thread observed latency and throughput. In this project we
present three new classes of thread fetch policies and we compare the
fairness and throughput of the new schemes with other proposed thread
fetch policies. Our results indicate that our Sliding Window Schemes
achieve a good tradeoff between the fairness and throughput for most
workloads, and it does so without degrading the performance
significantly.
Project Proposal
(pdf) (ps) (html)
Project Milestone
(Milestone1 Report :pdf)
(
Milestone1: slides) (Milestone1:
html)
(Milestone2: slides)
Final Project Report
(Report: pdf)
(Report:
html) (Slides)
Last Updated on 17:31 Dec 14 2003