We are approaching the end of a remarkably successful era in computing: the era where Moore’s Law reigns, where processing power per dollar doubles every year. This success is based in large part on advances in complementary metal-oxide semiconductor (CMOS)-based integrated circuits. Although we have come to expect, and plan for, the exponential increase in processing power in our everyday lives, today Moore’s Law faces imminent challenges both from the physics of deep-submicron CMOS devices and from the costs of both chip masks and next-generation fabrication plants. In recent years there has been intense investigation of technologies which hope to replace photolithographically manufactured CMOS as the basis for future computing devices.
One of the main reasons for the successes of the last thirty years has been the ability to effectively design and implement computing systems based on CMOS-based transistors. The relative ease of designing ICs is a combination of many factors including the elegance of the three-terminal CMOS transistor, the successful separation of circuit design and circuit manufacturing, and the combination of fabrication and manufacture inherent in photo-lithography. As VLSI technology pushes ever deeper into the deep-submicron regime designing circuits is becoming significantly harder. In fact, transistors no longer behave near the ideal, circuit design is becoming ever more entangled with manufacturing concerns, and the cost of fabricating the device is soaring.
There are many alternatives to CMOS currently being investigated. Many of these nano-based technologies were explored in a previously NSF-sponsored workshop, the molecular architecture workshop. For example, recent advances in molecular switches lead to the promise of nanocomputers extending Moore’s law beyond the end of the CMOS roadmap. The promise of computation being performed on self-assembled computers promises to help us breakthrough the lithography barriers facing the semiconductor industry. However, One of the main findings of that workshop is that nano-based design methodology needs to be investigated to more effectively promote the science and engineering of these alternative technologies. In this workshop we will explore how to more effectively engage computer scientists and electrical engineers in this process, so that research in the underlying technology can continue to make effective progress.
It should be noted that Nanoscience and technology is going to have a major impact not only on computing devices, but across a broad range of activities affecting the human condition in the 21st Century. Colloidal chemistry advances will lead to sensors that will finally achieve the long sought goal of outperforming a dog’s nose. New carbon nanostructures will lead to buildings stronger than anything built today but consisting only of paper-thin structures. Other opportunities have yet to be identified and exploited but are out there.
The proposed workshop is an outgrowth of the Molecular Architecture Workshop held at Notre Dame University in November, 2001. This proposed worskshop will have a set of more specific goals of establishing mechanisms and approaches for computer scientists and engineers to establish NanoSciences in fields such as Design Automation.
The purpose of this workshop is to answer the following questions:
Nanocomputers will have substantially different underlying structures than traditional computers. Can these structures be predicted sufficiently well to enable early design science research? For example, nanocomputers are likely to derive their complexity from highly regular structures, not large multi-functional ones. They are expected to require high degrees of defect and fault tolerance. The design sciences here could benefit from novel micro-architectural approaches, new approaches to massive ECC, etc.
The key question that we hope to answer is "What are the enabling abstractions that permit productive research on the design of nanoComputers without getting bogged down in the nanotechnology candidates?"
A traditional important focus area in Computer Science are the identification of new algorithms to solve difficult problems. There are potentially a number of computationally hard problems in nanotechnology that can benefit from such research. Possible examples include quantum engineering calculations, molecular behavior prediction in thin films, nanostructure property simulations in new carbon structures, and circuit simulations based on novel devices. We hope to determine an approach to identifying these problems and stating them in a fashion amenable for exposure to the CAD community.
While the physical science and engineering that enables NanoComputing
has made substantial progress, it is still undergoing rapid
change. This workshop aims at pinpointing the areas in which computer
scientists and electrical engineers can make the greatest contribution
to the continued progress in NanoComputing. This requires an
examination of the abstractions that support the design and
implementation of computer systems from circuits through programming.
Format
The workshop be held at Carnegie Mellon University over a three day
period covering October 16th, 17th, and 18th. The workshop will being
with an informal evening of October 16th. It will include all day on
the 17th and most of the day on the 18th. We expect that all the
participants will prepare a one-page position statement before the
workshop commences.
Below is a rough agenda:
| 10/9 | Submission of position statements by participants | |
| 10/16 | 7:00pm | Working dinner. |
| 10/17 | 9:00am | Introduction Introducing the goals of the workshop and some basic nanotechnology |
| 11:00am | basic science/engineering | |
| 12:00pm | lunch | |
| 1:00pm | talks | |
| 3:00pm | Group discussion: What are the issues? | |
| 7:00pm | Working Dinner | |
| 10/18 | 9:00am | Break into groups, produce some specifics that answer some of the questions that arose in the general discussion. |
| 11:00am | present results of break-out and refine focus. | |
| 12:00pm | lunch (Continue discussion) | |
| 1:00pm | Break groups to do some writing | |
| 4:00pm | Comments and refinement of writing | |
| 5:00pm | finish |
A block of rooms has been reserved for the meeting for the nights of Tuesday, October 15th, Wednesday, October 16th, Thursday, October 17th and Friday, October 18th at the following location:
When calling the hotel to guarantee your reservation, please inform them that you are part of the "NSF Workshop" since these rooms have been blocked in order for us to receive a reduced rate for this meeting.
To assist you in making travel arrangements we suggest you contact Irene at CTS International who will be able to help you book your flight, please call at 1-800-577-3665 or email her at cts@usaor.net.
Please mention that you are a NSF Workshop participant.
Directions from the airport to the hotel: Take route 60 south from the airport and follow the signs to Pittsburgh. This road will change names to I-279 west. Follow the signs to I-376 -- Monroeville exit. This will be the first exit on the right after travelling through the Fort Pitt tunnel. Take I-376 east to the Oakland/Forbes Avenue exit -- Exit 5. Once you exit you will be on Bellefield Avenue. Stay in the left lane and turn left on Fifth Avenue. Turn right at the next light. The Holiday Inn is located 1/2 block on the left. There is also a shuttle at the airport - direct to the hotel.
Parking will be a problem at the meeting location so it is recommended that you either walk or take the hotel shuttle. The Holiday Inn has walking directions at the front desk and has a shuttle to Carnegie Mellon every hour on the half hour..i.e. 7:30 am 8:30 am 9:30 am and can take you directly to Newell Simon Hall.
Newell Simon Hall, Room 3305: Through Entrance: 3305 is located on the
right hand side through double glass doors before you reach the
stairway.
Talks
Draft Report
Draft of report